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Is my design synthesisable if clock used as data?

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alam.tauqueer

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clock used as data

Hi,

can anyone tell My design is synthesisable or not if I use clock as data in our design.I n DC I am seeing it is not synthesisable but not able to get why it is not?

Regards
Tauqueer
 

n1cm0c

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clock used as data

all synthesis programs try to map your logic description to a SYNCHRONOUS logic model, where there's ONE clock line, and everything else is DATA. I think you should look for "clock gating" to find out possible work arounds and get DC to synthesize your logic...

btw ,ask this to the digital people, here is the ANALOG section...
 

Thinkie

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Strictly speaking your design IS synthesisable.....

BUT...

A) you will have some serious problems in STA and Clock Tree Synthesis

B) You will have problems in Scan Insertion and Pattern Generation..


... so.. you can do it... BUT DON'T DO IT..
 

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