By boss tells me that to get good matching in current mirrors they should be designed where L is large. My own understanding that as long as the devices are large in area and laid out well then they will match. So my question is length important or is making the area of the mosfet large sufficient?
Length is always important ;-). But you're right saying that device area is decisive for matching. The reason for designing current mirror transistors with (relatively) large length is: usually you don't want to spend large width just for current mirroring, so for matching accuracy you need larger length. And low W/L ratios achieve better simulation accuracy and lower Vds,sat , AFAIR.
Its related to the lambda parameter. Generally, in analog, longer MOSFETS are preferred.
Longer length also means r0 (r0 = 1/gds) is higher. Which is good for a current source. Also, if the resistance changes , it will be a much tinier fraction of what it would've been if the MOS were shorter. eg, if r0 is 1k and resistance changes by 100 ohm, its a 10% change. If its 10k, and it changes by 100 ohm, its 1%.
long channel length is related to both layout and the electrical properties of the current mirror.
for the electrical, long L will reduce the channel length modulation and hence increase the output resistance of the current mirror, as a result the current will be more stable.
for the physical (layout) properties, the large channel match better than the small channel because the variation on the wafer will averaged for the long channel while it is concentrated in the small channel, this make large different properties between the small channel transistors.
However we have ratio that is (W/L) and we have size (W.L), having long channel doesnt mean that you have small ratio because you can change the W as well.
for the current mirror matching you need large size transistors and small ratio to increase the overdrive voltage for better matching
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I think Erikl you wanted to say larger Vds
And low W/L ratios achieve better simulation accuracy and lower Vds,sat , AFAIR.[/QUOTE]
Hi,
For high speed circuits(>10Gbps) in tech. like 45nm or lower, we need to mirror current of the order of 3mA using programmable current steering DACs(which update at very low freq.) with the number of bits of the order of 7 or 8. Is it a good idea to have length of the main mirroring MOS of the order of 0.5um or even less with some cascade MOS with length 0.1um to save area? What else can be the smart ways to save area ?