Is it possible to simulate DNL and INL for a 10-12bit ADC?

[pablomilanes]

Simulate DNL and INL

chenliy, what kind of simulator did you use? spectre? did you need to use matlab to get INL and DNL?

For a top simulation of an ADC what are the paramenters needed to simulate?

 

[Karthikeya]

Re: Simulate DNL and INL

hi
i learnt tht to test INL/DNL of ADC by feeding its output to DAC ...then the resolution of DAC must be atleast 2-4 bits more than ADC's ...why is it so? can ne1 explain??
is it no possible to directly measure with same resolution?

information regarding INL/DNL testing is given in Analog Devices' Handbook

 

[chenliy]

Re: Simulate DNL and INL

pablomilanes, I use AMS simulation. AMS means Analog-Mixed Signal, that is to say Spectre-Verilog simulation. Yes, matlab is used with system simulation. For a top simulation of an ADC, the paramenters needed to simulate are static parameters (INL,DNL,Full Erroe,Offset Error, etc.) and dynamic parameters (SNR,SFDR,THD, etc.).


Karthikeya, "...then the resolution of DAC must be atleast 2-4 bits more than ADC's ..." is due to the accuracy of DAC more than ADC. For example, you
must prove accuracy of a ruler. You can use another ruler whose accuracy is more than the ruler measure it. Do you understand?

 

[Karthikeya]

Re: Simulate DNL and INL

hi

chenliy
must prove accuracy of a ruler. You can use another ruler whose accuracy is more than the ruler measure it. Do you understand?

but why only 2-4 bits is my question? why not, 1 bit?

 

[chenliy]

Re: Simulate DNL and INL

You can refer to Page 662 (Testing of ADCs) in CMOS Analog Circuit Design (Second Edition). The author are P.E.Allen and D.R.Holberg. ISBN: 7-5053-7758-2

 

[horzonbluz]

Re: Simulate DNL and INL

Thanks for you help, i will read these pages of Allen's book.

 

[gunturikishore]

Re: Simulate DNL and INL

Verilog-A or AMS can be conveniently used along with the circuit simulation to obtain the results simultaneously. There is a difference between measuring with actual circuit fabricated and measurements in simulation. I don't see any requirement for going to more number of samples than the actual sampling rate of the ADC or DAC while simulating. I made programs that run with 8 bit ADC in 6 hours with Cadence tools and I expect for a 10bit ADC at most a day or less than that.

 

[bitcat]

Re: Simulate DNL and INL

For INL and DNL, you really do not need a clock, I mean when you are testing for INL and DNL, you can put the clk to high(or low - depending on your configuration) and run a DC sweep.

?? Without the clock, how can your ADC / DAC works??

some configration,maybe.

 

[howardtang85]

Hey all,

I am using cadence-icfb to simulate my 10-bit SAR ADC.

I have noticed someone manage to simulate the ENOB, does anyone know how to do it in cadence?

Thanks!

 

[viral]

Check this out friends..

Communication Circuits Laboratory - UCLA

 

[horzonbluz]

Thanks a lot. I will see it.