Is it possible to replicate the functionality of a netlisted cross event in Verilog-A

[twix232]

Hello,
I'm trying to implement a prescaler block based on an algorithm.
The block should trigger a certain behavior when both signal1 and signal2 have rising edges.

// when a signal1 is in rising edge
@(cross(signal1 , 1)) begin
// check also when signal 2 is in rising edge but this checking should be second in priority which means when signal1 is in rising edge go check if signal 2 is in rising edge
    @(cross(signal2 , 1)) begin
        do something
    end
end

I have been searching for ways to create netlist-like events to achieve this functionality in Verilog-A, but I couldn't find any similar examples.
Can you provide guidance on how to approach this situation and implement the desired behavior?

 

[FvM]

By definition, events have no time duration. Respectively an AND operation that would never generate a trigger isn't provided by the language, the same as in "digital" Verilog.

I have difficulties to imagine which prescaler hardware small be modeled by an AND combination of clock inputs, please clarify.

 

[twix232]

By definition, events have no time duration. Respectively an AND operation that would never generate a trigger isn't provided by the language, the same as in "digital" Verilog.

I have difficulties to imagine which prescaler hardware small be modeled by an AND combination of clock inputs, please clarify.

multi modulus prescaler used in fractional dividers, it takes two input vco output the main signal that will be divided in the output of the presclaer and the second is delta sigma modulator that fed the presclaer with pulses that represent the fraction ratio)