OradFarez
Member level 1
Hello all. I am designing an 8 layer PCB. I can't afford to do it in 10 layers so there is one ground plane layer, one split up power plane layer and six signal layers that are stacked in a way that high speed areas can have a copper pour connected to ground on every second inner signal layer. It's not perfect, but it does provide extra shielding...at least I hope so. This is the stack up just for some clarification:
TOP - Components, slow signals primarily, some power traces
GND - plane
IN1 - high speed signals, very full
IN2 - high speed but large area for copper pour in area where fast signals are on IN1
IN3 - mixed speed, less area for ground pour
IN4 - mixed speed, moderate area for ground pouring
PWR - split plane, multiple supplies
BOTTOM - components, slow signals, some power traces
The thing I am wondering about is that since I have one pure ground plane and I want to lay down copper pours that fill in all areas of the board that do not already have copper on six other layers, do I risk making bad ground loops? Do such large continous pours help eliminate these problems due to lower impedances?
The board is entirely surface mount except for some connectors and the majority of components are BGA or QFN types. There are plenty of ground vias throughout the high speed area so I think loops are minimized.
What are other peoples experiences with this sort of thing? Thanks for any help.
TOP - Components, slow signals primarily, some power traces
GND - plane
IN1 - high speed signals, very full
IN2 - high speed but large area for copper pour in area where fast signals are on IN1
IN3 - mixed speed, less area for ground pour
IN4 - mixed speed, moderate area for ground pouring
PWR - split plane, multiple supplies
BOTTOM - components, slow signals, some power traces
The thing I am wondering about is that since I have one pure ground plane and I want to lay down copper pours that fill in all areas of the board that do not already have copper on six other layers, do I risk making bad ground loops? Do such large continous pours help eliminate these problems due to lower impedances?
The board is entirely surface mount except for some connectors and the majority of components are BGA or QFN types. There are plenty of ground vias throughout the high speed area so I think loops are minimized.
What are other peoples experiences with this sort of thing? Thanks for any help.