Is it possible to have a negative Vs in NMOS?

[iVenky]

Consider an NMOS. Is it possible to have a negative Vs while the device is in saturation or in linear region. I mean all other conditions such as Vgs > Vt and such kind of conditions are satisfied with the exception that Vs is negative. Is this possible?

 

[barry]

Vs is negative with respect to what? Vg? All the Mosfet cares about is the RELATIVE voltages (Vgs, etc.) It doesn't care about the 'outside world'.

 

[checkmate]

Unfortunately, things get a little bit more sophisticated if the body is tied to gnd.

 

[iVenky]

Vs is negative with respect to what? Vg? All the Mosfet cares about is the RELATIVE voltages (Vgs, etc.) It doesn't care about the 'outside world'.

Vs is negative with respect to ground. Also Vgs is positive so that the device is on.

---------- Post added at 08:05 ---------- Previous post was at 07:34 ----------

Unfortunately, things get a little bit more sophisticated if the body is tied to gnd.

Yes. The body is tied to ground. Then the source and body becomes forward biased and the current will start to flow through the substrate


You just tell me if this is possible----
The transistor has come to this state because of the configuration of the circuit in order to make sure that the device is on(due to cause and effect).