Is it possible to clone of the XDS510PP (TI DSP emulator) ?

[aberro]

Re: Is it possible to clone of the XDS510PP (TI DSP emulator

Hi, i tried the the xds510pp with smc34c60 implemented in vhdl. But i used a spartan 3 development kit, with two selfmade board connected to it. One with buffers and a db25 parallel port connector and the other with the tbc 74act8990, buffers, and the 14 pins jtag connector. I didnt used a gal because i included the equations into the fpga. Then i proved it with a vc33 board and sdconfig generated scan errors in diagnostic mode. The clock was in the start 8.33 MHz and was generated by the fpga dividing by 6 its 50Mhz clock. I reduced it ti 1.56MHz and the rate of errors was reduced. Then as i thinked there was a problem in the form of the clock wave i added an schmidt-trigger inverter at the clock output and the error rate reduced again, now it is 2 errors each 2000 tests. I execute code composer and i can load a program if it is small (4Kb) and sometime trying more than one time because it reports memory verification errors. But i can't set break points or execute.
I think there is a sinchronization problem but i haven't any idea to fix it.

Added after 1 hours 50 minutes:

Someone knows the function of signals EMU0 and EMU1 in the jtag connectors?

 

[aberro]

Re: Is it possible to clone of the XDS510PP (TI DSP emulator

If i use the next implemantation of the gal equations in the fpga i obtain 1 error / 100 tests in sdconfig. The delay of 2 cycles in the capture od TDO and TMSO in the process are important, but i don't know why. Does anybody explain me what exactly must do the gal?, I am know lost and confused.

-- ecuaciones de la pal
process(clk)
begin
if(clk'event and clk='1') then
if(divisor=0) then
bclk <= not bclk;
divisor <= "00001111"; --50Mhz / 32 = 1.33MHz
elsif(divisor="00001110") then
if(bclk = '1') then -- positivo edge
io15 <= TDO;
io13 <= TMSO;
else -- flanco negativo
TMS_aux <= io13;
TDI_aux <= io15;
end if;
divisor <= divisor - 1;
else
divisor <= divisor - 1;
end if;
end if;
end process;


jtag_TRST <= (not hpi_cs) and TBC_INT and (not TMS5);

jtag_TMS <= ((TMS_aux and pp_cs2) or (io13 and (not pp_cs2))) and TBC_INT;

jtag_TDI <= ((TDI_aux and pp_cs2) or (io15 and (not pp_cs2))) and TBC_INT;


TCK1 <= bclk and TBC_INT;

 

[pupzemly]

Re: Is it possible to clone of the XDS510PP (TI DSP emulator

арполпи тждджждп ддирди

 

[iolio]

Re: Is it possible to clone of the XDS510PP (TI DSP emulator

DLE500USB

USB JTAG-emulator DSP TMS320

TMS320C64x, TMS320C55x, TMS320C28x

based on AT91SAM7S64

 

[arm123]

act8990 datasheet:
**broken link removed**

 

[arwei]

I am also trying to write a verilog 8990

Added after 2 minutes:

www.verilog.org

 

[oak100]

ok,ok!