Is it possible that Vera work with NC-verilog/vhdl ?

[DeepIC]

Vera & NC-sim

hi,all

Is it possible that Vera work with NC-verilog/vhdl ?

 

[weilijun]

Re: Vera & NC-sim

Maybe NC-sim can support vera through PLI?

 

[cnspy]

can you point me how to ?

 

[Richardlin0301]

Re: Vera & NC-sim

vera is belonged to synopsys.
ncsim is belonged to Cadence.
It stands to reason.

 

[mexico_mike]

Re: Vera & NC-sim

I'm using VERA now with Modelsim and VHDL, and I think it does support NC-SIM.

 

[cyc]

Re: Vera & NC-sim

hi,all

Is it possible that Vera work with NC-verilog/vhdl ?

Refer to Vera's documents.
There is a step-by-step guide to compile the PLI for NC-Verilog.

 

[wang1]

Re: Vera & NC-sim

hi,all

Is it possible that Vera work with NC-verilog/vhdl ?

Yes they can co-work via PLI, but the speed is very slow.

So if you wanna use HVL, try "specman + any digital simulate" or "vera

+ vcs".

 

[mami_hacky]

Vera & NC-sim

Is this also true for Vera 6.2 ? I'm wondering if there exist a simple way for making connection between Vera 6.2 and LDV 5.