LDMOS are meant for switching and so are
probably intended for Class C, Class E type
PAs which tend to have tuned output match
transforming the pulsed waveform into a
single (passed) frequency out the back.
That (tuned load) fights against wide and flat
amplifier bandwidth / response.
LDMOS are good for high blocking and low
on resistance, but not at the same time -
power dissipation within the core device
is highly concentrated / uneven and the
same power handling, steady state, per
die area may be less than a device with more
uniform and less interconnect-adjacent
(like vertical) heat-throw by construction.
What you "can get" in simulation, and what
the hardware can survive, are separated by a
gap in knowledge and modeling and post
analysis (like temp rise at the drain contact
and the metallization above, vs junction temp
dependent lifetime, from electrical / thermal
TCAD or direct measurement at microscopic
scale (such as an IR camera microscope)).