Is it good to connect signal to the clock pin of flip-flop ?

[ftian]

Is it good or not?

Is it good or not if I directly connect a normal signal, not clock signal, to the clock pin of flip-flop?

That happenes if I want to monitor an input pin's falling edge, or I should use system clock and two flip-flops to do that...

 

[eda_wiz]

Re: Is it good or not?

Is it good or not if I directly connect a normal signal, not clock signal, to the clock pin of flip-flop?

No asynchronous design methodologies are generally not recommended. as its not friendly with STA and DFT

That happenes if I want to monitor an input pin's falling edge, or I should use system clock and two flip-flops to do that...

do u want to detect the edge or the signal value.. explain the situation in detail

 

[ftian]

Re: Is it good or not?

do u want to detect the edge or the signal value.. explain the situation in detail

I want to detect edge.

 

[yuzhicai]

Re: Is it good or not?

do u want to detect the edge or the signal value.. explain the situation in detail

I want to detect edge.

So, you can use a edge detect circuit which can use level to replace edge.
Like this:
// detect the posedge of q
always @(posedge clk)
q_dly1 <= q;

assign q_posedge = q & !q_dly1;

 

[troops]

Is it good or not?

it is not better as u do STA and DFT ....
it is hard to do above work 0...

 

[lionhunter]

Re: Is it good or not?

You need to consider the driving, glitch, test and synthesis issue. If they are all ok to you, you can use it.

 

[tom123]

Re: Is it good or not?

I think that's a bad idea. because it is not good for synthesis, it not good for DFT,

it's not good for timing analysis. but if you want to lower power consumption

through this method, that's good.

Is it good or not if I directly connect a normal signal, not clock signal, to the clock pin of flip-flop?

That happenes if I want to monitor an input pin's falling edge, or I should use system clock and two flip-flops to do that...

 

[Karthikeya]

Re: Is it good or not?

yuzhicai

So, you can use a edge detect circuit which can use level to replace edge.
Like this:
// detect the posedge of q
always @(posedge clk)
q_dly1 <= q;

assign q_posedge = q & !q_dly1;

this works only when the clk is high ...wht happens if input changes when clk is low
how to do a synchronous design for this???

 

[amarnath]

Is it good or not?

instead of posedge use negedge and then use the same code,this is for verilog,for vhdl u can do it like:

process("sensitivity list")
if (clk'event and clk=='0')then


regards
amarnath