Is it easier tune cut-off of FET harmonic generator for bigger input voltage swing?

[Terminator3]

Some theoretical thoughts. Now i am looking at https://www.minicircuits.com/pages/pdfs/dg03-110.pdf.
For example,
0dbm -> 0.225 volts
+20dbm -> 2.25 volts
I am not sure what volts here is, AC amplitude or something else. Anyways the more power we have, the bigger sine amplitude is.

It looks that tuning 0dbm input multiplier would be more difficult, because output will be too small:
Small error in gate voltage will lead to big error in choosing point where sine must be cut off. Temperature changes, etc. will impact amplifier tuning heavily. For example, error of 0.2volts will make multiplier useless.

When using +20dBm or so, voltage swing itself is big, so even huge error of 0.2v will not tune-out multiplier out of working values.

So is it true, that when we have more input power, it is easier to tune multiplier for desired N harmonic for cercain cut-off time?

 

[jiripolivka]

Some theoretical thoughts. Now i am looking at https://www.minicircuits.com/pages/pdfs/dg03-110.pdf.
For example,
0dbm -> 0.225 volts
+20dbm -> 2.25 volts
I am not sure what volts here is, AC amplitude or something else. Anyways the more power we have, the bigger sine amplitude is.

It looks that tuning 0dbm input multiplier would be more difficult, because output will be too small:
Small error in gate voltage will lead to big error in choosing point where sine must be cut off. Temperature changes, etc. will impact amplifier tuning heavily. For example, error of 0.2volts will make multiplier useless.

When using +20dBm or so, voltage swing itself is big, so even huge error of 0.2v will not tune-out multiplier out of working values.

So is it true, that when we have more input power, it is easier to tune multiplier for desired N harmonic for cercain cut-off time?

It sounds strange that you have no knowledge about the basic relations of power and voltage while trying to "design a frequency multiplier".
Please learn the basics, THEN try to do more complex things. Your questions do not cover what exactly you are trying to do. Then it is impossible to offer any advice.

 

[Terminator3]

Whywhywhy you doing this? let's make you happy

p=(1*10^(0/10))/1000
p = 1e-3
p=0.001
p = 1e-3
v=Sqrt(0.001*50)
v = 2.236067977e-1

p=(1*10^(20/10))/1000
p = 1e-1
p=0.1
p = 1e-1
v=Sqrt(p*50)
v = 2.236067977e0

I think i must simplify my question.
We have a potentiometer connected to negative supply, slowly turning potentiometer in one or in another direction, changing biasing of FET's gate.
If gate's input AC is small in amplitude, then even little change in gate's biasing can put whole AC wave in cut-off region.
If gate's input AC is big in amplitude, the same change in gate's biasing can'not put AC wave in cut off region.
Is it correct?

Illustration for clarification:


So if input is not enough in power, then temperature impact on gate biasing can move whole sine in cut-off region and output become silent, and following amplification stages useless?