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Is is necessary to include a counter under MOD???

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khaila

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Once, I noticed that counter of 4 bit implemented in VHDL while

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signal counter : integer range 0 to 15;
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elsif clk'event and clk = '1' then
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counter <= (counter + 1) MOD 16
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is it necessary???
Does this MOD promote the synthesizer effort???
 

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