is internal memory allowed in FPGA

[samuel_raja_77]

i need to have memory in my design is it possible to have internal memory of some 10K in fpga or we need to have only external memory ........i am using xilinx version 8.1i and the device i choose is virtex - II pro xc2vp7 which has the 11,088 logic cells
792 BRAM(Kbits) 44 (18X18) multiplier ...........help me with some suggestion

 

[vahidkh6222]

yes i think u can use BRAMs(if they were sufficient for ur design). actually they ARE using for these purposes. you can even use them as some kind of ROM memory. if you initialize them with ur constant data.

 

[samuel_raja_77]

1.Does these ROM and RAM need to be codded as a separate module .........i.e. if i have a RAM of 2K is it strict to be placed as a separate module or i can use them in my already existing module with another always block......
2.if i have a RAM within in the module as another always block how to access........it please help...me in fixing the design with some suggestions,................

 

[deh_fuhrer]

You can use in your module.
First declare a reg of required size.Then declare a pointer which can read or write the memory.When writing the memory increment the pointer on each clock edge.
e.g.

for writing
input in;
mem[0:1023];
always @(posedge clk)
begin
i=i+1;
mem=in;
end

for reading simply point as mem[34] or whatever location you want.

 

[salma ali bakr]

so, one can have memory initialized within the HDL design as an array
or use also separate memory provided in the development kit

correct me if i'm wrong please

 

[Iouri]

You can use BRAM or if you have extra LUTs in your design you can use as memory as well

 

[darylz]

BRAM is available in fpga. but behavior level description will not work. pls refer to mannul

 

[vahidkh6222]

you have the full optionality in this case.
you can make a seperate module as MY_RAM and define its behavior and access to its ports just like an external ram.
or u can define ram inside your design very simply. for example for a dual port BRAM we have:

process (<clock>)
begin
if (<clock>'event and <clock> = '1') then
if (<enableA> = '1') then
if (<write_enableA> = '1') then
<ram_name>(conv_integer(<addressA>)) <= <input_dataA>;
end if;
<ram_outputA> <= <ram_name>(conv_integer(<addressA>));
<ram_outputB> <= <ram_name>(conv_integer(<addressB>));
end if;
end if;
end process;


from this moment on, if u wanted to read smthing from specified address, you must adjust "addressA" with intrested adresa and then put '1' in "enableA" signal. the requested data is ready on "ram_outputA" on next clock edge. and if you want to write somthing provide the addreassA and input_dataA with intrested data and then put '1' on the "write_enableA" signal....