dhasmana said:What is the DC voltage on the Pin/pins u need to put ESD structure?What is the Chip power supply?Do you have Zener diodes in that technology?
transbrother said:prcken,
THe first step I would take is to find out the different junction breakdowns and see if they are modelled in the process whereby you are performing this study. You can then worry about using these different junctions for protecting circuits.
transbrother said:prcken,
As far as modelling the ESD device, if you can get access to verilogA or verilogAMS you could try writing a behavioral model for the ESD clamp. It shouldn't be that difficult. For e.g. you can start with writing some simple BJT models defined in both rev. and fwd active mode. Now that you are able to simulate the 'substrate pump NMOS' you could repliacte its behavior in the verilogA model, use this as a starting point to then improve upon it.
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let me know how it goes.
For starters take an ideal diode.
Connect terminal A of a resistor in series with the anode of the diode. Connect a voltage source (positive end of the source) to the cathode of the diode. Make the voltage source = 20V, resistor = 1kohm. the other end of the voltage source can be at gnd.
When you sweep the terminal B of the resistor from 0 to 40V, and measure the current across the voltage source, you can see a breakdown-like curve whereby you have small current till you get to 20.7V, and excessive current past this voltage.
You can then get creative and see if you can get a exponential behavior (as opposed to a linear behavior in this case), of the current. Then, you can add some timing information like adding caps, etc. Also later on you can try to add some leakage currents.
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