Is default required for fully covered CASE statement

[Guru59]

hello all,
is default case required for a fully covered CASE statement in verilog

eg :
case(state)
2'd00 : y<=a;
2'd01 : y<=b;
2'd10 : y<=c;
2'd11 : y<=d;
endcase

thanks

 

[kujigaya]

No =)

another way to code this is change the last case as the default case.

case(state)
2'd00 : y<=a;
2'd01 : y<=b;
2'd10 : y<=c;
default : y<=d;
endcase

this way you'll still
- pass syntax checker tools such as Leda or Spyglass (which require a 'default')
- prevent unhit lines during code coverage (if you specify all 4 cases and still add a default)

 

[bapodradhairyab]

not required for fully covered case but it is good to practice with default mapped to idle or initial state...

as some simulation may not understand with out default but it is not requirement it is issue when u more number of cases where some case might not covered and for that if you keep it in practice you will never make mistake...

 

[kujigaya]

not required for fully covered case but it is good to practice with default mapped to idle or initial state...

as some simulation may not understand with out default but it is not requirement it is issue when u more number of cases where some case might not covered and for that if you keep it in practice you will never make mistake...

I agree on the "keep it in practice" =)

This is one way to avoid latches during synthesis or hanging state machines

 

[FvM]

This is one way to avoid latches during synthesis or hanging state machines.

Most likely it isn't, depending on your synthesis tool. State variable values, that are not set anywhere in your code are typically
removed from case decoding by the HDL compiler. So the default statement, as far it concerns illegal states, is simply ignored. Some
design tools have special "safe state machine" synthesis attributes to generate extra code to escape from illegal states.

But it's suitable to achieve a full decoding of existing "forgotten" states and can prevent unintended latch inference.

 

[gurucharapathy]

In case of verilog, the variable reg/wire would have four possible states: 0,1,z,x.
So I assume the default statement is still needed to take care of the x,z conditions in simulation.

Any thoughts about this ?

 

[raghava]

HI,

Its good coding approach to have default statement which always shows start state even though we have covered all states.

Did I help you.???

Regards

 

[ASIC_intl]

hi gurucharapathy

The default statement is still needed to take care of the x,z conditions in simulation. But is not this default statement is still needed to take care of the x,z conditions in SYNTHESIS?

Regards

 

[wsong0210]

a real hardware signal does not have X state. Z appears when open-drain circuits are used but this only happens on I/Os.
In other words, synthesis does not care about X or Z in case statement.
When all 0/1 cases are covered, there is no need for a default case.
However, adding a default case to a fully covered case statement is fine. It will be ignored by the tool.