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ir2110 low side problem

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mshh

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i tried t he attached circuit ,ir2110 low side output is same as high side . i saw it on oscilloscope. R13 got hot and burnt, i used the circuit without connecting the meter this is the only difference . supply to the circuit is around 10v also the pll isn't affected when changing resistor value on Vcoin pin what is the problem ?
 

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asdf44

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Just do one step at a time...remove power from the half bridge so nothing can burn and take your time studying the gate drive signals at each step. Going into the driver, coming out of the driver etc.
 

mshh

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signals to the driver are the same.Is this mean the 7402 ic is the problem?
 

KlausST

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Hi,

As always with power switching applications: PCB layout is critical.
Especially if you not experienced I recommend to use one layer of the PCB as GND plane ... no other signals.
And use proper decoupling capacitors.

One problem that I see with your circuit is that there is no dead time control.

Did you read the IR2110 datasheet and the application notes that are freely available at the manufacturer's internet pages?

Klaus
 

wwfeldman

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signals to the driver are the same.Is this mean the 7402 ic is the problem?
signals to the driver are the same as what? each other?

the sequence should be both sides off / low side on / both sides off / high side on / both sides off / etc

your drive circuit appears to be low side on / swap low off high on / swap low on high off / etc
which means both FETs can be on at the same time, during the swap
hence the current sense resistor R13 is tied across the output of the bridge
about 120 V RMS across 0.33 ohm, so it burns up

what does the output go to? there is no feedback to control the output voltage.
 

asdf44

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signals to the driver are the same.Is this mean the 7402 ic is the problem?
Yes, you can't blame the driver if its being told to turn both fets on. So debug your logic, you're sure its the right part and the right pinout etc? Thinking about it really quickly the logic makes sense to me.


Klaus the deadtime is in the pot+C on the gate inputs.
 

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Put 10uF on Vdd right by the driver, the logic seems OK - but check without the top drain connected on a scope to be sure you have dead time.
 

mshh

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I noticed that Hin and Lin are high at the same time and low at the same time however I simulated it on proteus and they were different and it worked as expected

- - - Updated - - -

What do you mean top drain connected? The driver is good I think the problem in the logic it should output one different from another
 

Akanimo

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Hi,

There is certainly an issue with the 7402 gates arrangement. There is a shorter propagation delay from the 74HC4046N to Lin than there is to Hin. So there leaves an interval at transition where Lin sees a new signal but Hin is yet to see its own.
 

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C 8 & C9 may be too small for useful dead time - if you disconnect the top drain you can run the driver IC correctly without blowing fets and see the correct gate drive on the fet gates ... i.e. the bootstrap in the drive IC will work ...
 

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You can use the gate on the 4046 to do the inversion - and get the two signals, then use the inputs to the IR2110 for the RC delay at turn on - this would reduce your parts count and is more robust ...

- - - Updated - - -

i.e. take pin 14 high, connect pin 3 to 4, then pin 2 is the inverted GD and pin 4 is the non inverted.
 

mshh

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- - - Updated - - -

i.e. take pin 14 high, connect pin 3 to 4, then pin 2 is the inverted GD and pin 4 is the non inverted.
pin 14 of what. which IC do you mean?
 

mshh

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do you have any application or schematic for your proposed connection?
 

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Why yes, I have used it to control a 3kW telecom power supply, 200kHz - 400kHz ( no load ) parallel loaded resonant converter, 42-60VDC out at 50ADC. ( no IR2110 though, gate drive emitter followers and transformers ).
 

mshh

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Is this reliable, or it will face problems in future?
 
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mshh

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it worked on proteus but it didn't work on pcb
 

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