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ir drop.....how the reduced voltage affects timing ?

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subramanyam

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Hii,

bcoz of the IR drop , in submicron technologies the supply voltage at the affected gates will become lesser.But i didnot get how this reduced suply voltage causes timing violations ??

plz any 1 help me,

regrds,
subbu
 

I got the answer for this.

As the rise and fall times depend upon the supply voltage , it will affect the speed .
 

IR drop is caused by the sheet resistance of the interconnect. You must use the calculation R = (pie/ t)*(L/W) = Rs * (L/W) to calculate the voltage drop between two points. The sheet resistance can be provided by the fab/kit/design rules. A good layout engineer will know this off by heart!

This can be improved by either using W I D E R metal to increase the amount of squares OR carefull floorplanning would minimise., heance the reason why floorplanning is so important!...
 

the cell delay will increase as the supply voltage is decreased.
BR
 

time = \[\frac{charge }{current }\]

charge = Capacitance * supply voltage

current = (\[\frac{\mu*Cox*W}{L}\])* (\[{ (VDD-{ V}_{t })}^{2 }\])

Therefore time is inversely proportional to the supply voltage. When the supply voltage decreases due to IR drop, the cell rise and fall time increases so the cell delay increases which leads to setup-hold violations.
 

Hi,

In simple .. charging and discharging variations are reflected as rise and fall time increase by the IR drop..

Thanks..
 

The I*R drop is going to be time-varying and data-
varying, and you are not concerned about only the
time-averaged "I" but its worst case dip at exactly
the wrong time - this will be your outlier delay and
the extent of timing nondeterminism.

For example, a logical event that causes chip scale
switching will hammer the bus far beyond normal
averaged small scale switching current-slugs. To
get timing signed off righteously, that minimum Vdd
span (and you must also include VSS internal I*R
rise), your rail span collapse is

(Vdd0-Vss0)-I*(Rvdd+Rvss)+dI/dt*(Lvdd+Lvss)

or something like that and it needs to be better than
the Vdd (Vdd-Vss) assumption in the timing models
or the timing analysis is rendered bogus as far as
design integrity proof goes.
 

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