jaya sree
Member level 3
hai everyone ,
we see setup , hold clock gate , io-flop , flop-io and io-io etc violations and issues in timing analysis . can anyone provide me any material regarding what must be done and observed during power analysis. what are the different issues.any document will help a lot. i use apache and pt tool for ir drop analysis.
we see setup , hold clock gate , io-flop , flop-io and io-io etc violations and issues in timing analysis . can anyone provide me any material regarding what must be done and observed during power analysis. what are the different issues.any document will help a lot. i use apache and pt tool for ir drop analysis.