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IR drop analysis , power analysis at tile level

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jaya sree

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hai everyone ,

we see setup , hold clock gate , io-flop , flop-io and io-io etc violations and issues in timing analysis . can anyone provide me any material regarding what must be done and observed during power analysis. what are the different issues.any document will help a lot. i use apache and pt tool for ir drop analysis.
 

jaya sree

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does ir drop analysis needs def as input ? or netlist and spef is enough ?? I would like to know how ir drop analysis is done at p & r stage.i am using synopsys tool.i am unable to understand what issues , reports must be observed. please help
 

sathyanarayana raoh

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hi jaya sree,
ir drop is mainly occurs due to the increase in resistance.this effect is more for lower technology like 40,28 nm technology. the reason is as the shrinking of technology due to this the wire length is increased and wire thickness is also increased to improve s.i ... as wire length is increased
as we know R=pl/A
R is directly proportional to length... this is the main reason for increase in ir drop....

in soc we got to give pad location file.. in power analysis and from there we vl use voltage strom2 for power calculation.. there we vl get power.db file...we have to give these two as inputs for ir drop analysis..actually there will be auto filters (range) voltage....according to those colours of that filters it vl show ir drop in our core.
hope this link help u how we can actually calculate ir drop.....
thanks



IR-8
 

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