This is example of block RAM from ISE coding templates :
parameter RAM_WIDTH = <ram_width>;
parameter RAM_ADDR_BITS = <ram_addr_bits>;
(* RAM_STYLE="{AUTO | BLOCK | BLOCK_POWER1 | BLOCK_POWER2}" *)
reg [RAM_WIDTH-1:0] <ram_name> [(2**RAM_ADDR_BITS)-1:0];
reg [RAM_WIDTH-1:0] <output_data>;
<reg_or_wire> [RAM_ADDR_BITS-1:0] <read_address>, <write_address>;
<reg_or_wire> [RAM_WIDTH-1:0] <input_data>;
always @(posedge <clock>) begin
if (<write_enable>)
<ram_name>[<write_address>] <= <input_data>;
<output_data> <= <ram_name>[<read_address>];
end;
So input_data is your output result of your program.
If later you are going to use your stored data in random order, use RAM type above. If you are going to use your data in sequential order, try to use FIFO(xilinx offer core in CoreGen), it is more simple in usage.