stackprogramer
Full Member level 3
IP core (Verilog or VHDL code) in Xilinx and Vivado is open source or encrypted?
I had a question how much I can determine whether the IP core is encrypted or Verilog code is open to editing?
I attached an IP core that is built in the synthesis can you guide me that this IP core source is open?
I was faced with some strange lines. Is this IP core source encrytped?
...
I had a question how much I can determine whether the IP core is encrypted or Verilog code is open to editing?
I attached an IP core that is built in the synthesis can you guide me that this IP core source is open?
I was faced with some strange lines. Is this IP core source encrytped?
Code:
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
eD8hpFSXjd1TN/qwD6KGU+z2509uzOtDyaItcj8UJV6/9IqXwmzXm49sQewLHmPx+zfD6FQpyw+p
h0cjnBe4og==
`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
L3SB3aFsPoBeCHEa+GJTxCywCdtSUeC6UY906VBmK5CfzTgqgVyM79kYm6BdXD2tikY3hMRbv08+
R63jVwCpRcJdeLJIbr58+pkInrN5jPNeOMVT4fdRP6mG/A+kbgolgF+LCX4UlGa6A14h5xUJIQ+I
BOJCodJ7zf2U3UPN5i4=
`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
IDpiTi+KiM/mIyaieWhkLwbuAoWvynL5XwxHTZc9uzTfzudCoilyQ4oKu2/PRnV4HtTBM1PW4epl
rd9LP+loq5H8NbcXKhoN4VzhEypgVleSbFixkcTkk7Osf7hVTnIQPy+t0WVEWaONYL5atSlOleSA
iLuTn53tMAhqoF+UIInXe7RC0RJ3+CAVLKs9w091HN93vVUPCig/wIe/MmVL56SzFtGO/87XTi/+
qJFEM7WvagMWeW2rwVCOs/gjJhh8s+7tB2d3KXQb0D4ZLH7wYYzzwMxpSMKY/l9qmmdLA/pN12/C
iPZ8yl6wlb49sIPVnHi7OqJQ2eGqj1d8h/GCTA==