I think there are SRAM controller IPs provided by Xilinx. Assuming you have the proper license, a controller memory IP can be generated which might have various interfaces to interact with the outside world.
e.g. The DDR3 SDRAM controller IP core can be generated with can either have an AXI4 interface or User Interface (UI) or the Native Interface.
You just have to make a self-study as to which interface suits your environment the best and then generate the IP accordingly.
Dear Mr. O.P. please play around with whatever Xilinx s/w you are having and read some docs using the "DocNav". Most of your answers will be there. Members here cannot search out or suggest IPs to you since they are are ignorant about your design environment.