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Not an expert but I hope a few tips below help:
1. check if the violation is of a valid path. For example: is the start & end clocks (also clock edges) proper? is this path functionally valid? This requires front end or RTL or functional knowledge towards the design.
2. check clock skew. Make sure it is within your acceptable range.
3. check whether the path has large transition time. Large transition time commonly caused by long net without buffer, and it will badly affect the setup time.
4. check whether the path contains excessive/big buffers.
Also, pls check if the violations at very huge scale with huge slacks? (e.g: multiple violations with slack of few ns each) If yes, you might want to double check high-level root cause, such as clock skew (clock implementation), constraint setting, P&R setting, etc. Else you may investigate at individual path level.
Quick things to look at apart from what "chids" has mentioned:
1. Look out for High Fan-out nets
2. Look at the levels of logic created by the synthesis tool, correlate that with your RTL code and see if you re-write in a better way so that tool can implement it in a better way
3. Look at the constraints, whether they are correct/realistic, some paths may require multicycle path constraints because of the logic(Example : Adders, Multipliers)
if you have explict logic where you want to improve the timing, post it up so that some new ideas can come pump in by the members
Ya you are right.. you can replace with higher driving strength cell also. You can also divide your net into 2 parts. means half of the nets are driving by 1 cell and other half by other cell (of same type). There are lot of ways to solve this type of problem but those depends on your design / specification / design constraint and all. But in general these 2 are best.
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