Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

inverter delay with slow ramp input

Status
Not open for further replies.

irfansyah

Advanced Member level 4
Joined
Dec 29, 2004
Messages
106
Helped
9
Reputation
18
Reaction score
1
Trophy points
1,298
Location
New South Wales
Activity points
1,128
inverter ramp input

hi, i wonder if anyone can help me with this "inverter delay measurement" problem i have.

Normally, textbooks define inverter propagation delay to be = RCln(2), which is the time interval between 50% change in input to 50% output change (CMIIW). Apparently, this formula is only good for very small input rise/fall time, and fails to predict inverter delay if slow ramp input is used.

One thing odd that happens when i measure propagation delay according to the above definition is that i can actually get a NEGATIVE value of delay (50% output happens before 50% input), particularly when input is slow and output is very lightly loaded. So i simply changed the way i measure delay to be the time interval from output's initial value to 50% change of itself. BUT, the values i get becomes way off the estimated delay according to the above formula when i use it with fast rising/falling inputs.

Hence, here are my questions:
1. Am I doing the right thing when i measured propagation delay to be time interval between 50% change of input to 50% change of output?
2. Are there any simple yet widely acceptable formula to estimate inverter delay with slow ramp input?

Many thanks.
 

Fahmy

Full Member level 2
Joined
Mar 21, 2007
Messages
132
Helped
28
Reputation
56
Reaction score
12
Trophy points
1,298
Activity points
1,973
getting -ve value for the delay based on 50% input to 50% output is not strange . This case will likely happen when the inverter threshold (according to DC c/cs) is less than Vdd/2 and the input is rising from low to high or when the threshold is greater than Vdd/2 and the input is falling from high to low. These two conditions will cause the output to reach Vdd/2 point before the input , given very slow input.

I don't think it is right to measure delay to be the time interval from output's initial value to 50% change of itself. Thi way will give you about half the rise/fall time not the propagation delay.

you can think about using the dc c/cs to estimate the delay and you must accept -ve values.
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top