# Inverter Chain Synthesis Problem

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#### davyzhu

inverter chain synthesis

Hi,

I work on Xilinx ISE, and my synthesis tool is XST and synplify.
I use verilog to write a Inverter Chain (delay ) like out = ~(~(~(~...in)).
But the circuit be synthesised cancel all the invorter.

How to synthesis out all the inverter chain I want?

Any suggestions will be appreciated!
Best regards,
Davy

#### echo47

You need to declare individual wires for each signal (not just a boolean expression with lots of ~ operators), and then use the KEEP constraint to prevent XST from optimizing them away.

Code:
module top (in, out);
input             in;
wire        [7:0] delay;  // synthesis attribute KEEP delay TRUE
output            out;

assign delay = ~{delay[6:0],in};
assign out = delay[7];
endmodule
Why do you want such a thing? Delays are usually something to avoid.

### davyzhu

Points: 2

#### davyzhu

Hi echo47,

Thank you

My friend want to generate a random data generator. And he need a delay loop.

Do you think what's the best way to get delay in FPGA (delay smaller than one clock period)?

Best regards,
Davy

#### echo47

I'm curious -- how will a delay help you build a random data generator?

Delays are usually bad things. Try modifying the design to eliminate the need for delays.

If you really need a half-clock delay, or a third-clock delay, or something like that, then I would consider using a frequency multiplier (such as Xilinx DCM) to increase the clock frequency, and then use it to clock a small shift register that delays the signal.

#### davyzhu

Hi,

Ah, I read a applicatoin note about digital PLL from Xilinx. They use MUXCY (fast carry chain) to build a more precise comb delay in FPGA.

As for random data generator, I don't know how to generate it in digital way. Any my friend said it's a secret :-(. Do you have any idea?

Best regards,
Davy

#### echo47

You can't built a true random number generator digitally.

You can build a pseudo-random number generator digitally. For example, a simple linear feedback shift register (LFSR) outputs a pseudo-random bit stream:

There are countless other pseudo-random number generators of varying quality. Search Google.

Points: 2