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The main problems are (1) a single supply and (2) a bad
dependence of supply current and output swing on input
Figure you need the supply to be the upper voltage of
the desired logic swing at the output. If the output is
(say) 0-5V and the supply is then also 5V, and you
(say) wanted to give it a 0-2.5V swing on the input,
the low input state will be fine, but the high input
will put the inverter linear, eat a lot of current and
put the output midrail, not in its desired logic state.
For the higher-to-lower case, your main issue would
be the input ESD protection (given that, again, supply
is the output VOH level, then VIH > VDD by definition.
An internal (not pad exposed) application, you could
do this though (overdriving the gate) subject to the
device reliability application rules.
I reminded myself today that the 74HC series can act as good level shift down to Vcc of 2 to 6V.
They were designed for CDxxx series with an input threshold of Vcc/2 but have a polysilicon input R and clamp diode to Vcc so it can handle any input up to 16V.
Since CMOS has a near zero static bias current, the typical voltage and current margins are good from CDxxxx series with 200~300 Ohm driver impedance or other logic families with much lower driver impedance , with each generation going down to 100, 50 and now 25 Ohm.
The measure of noise immunity for stray capacitive voltage and inductive coupled current is the impedance ratio at speed of transition from source to signal impedance. This determines how many mV's of noise is coupled into the signal. Normal f is 3x Trise and crosstalk capacitance can be tested or analyzed.
There are many other level shifters that are design to perform this as well to lower levels. The most crucial time is often during switching of edge counting logic, where hysteresis input gates are preferred for long inductive tracks or better use controlled impedance tracks. But interboard signals may be in doubt.