amburose
Junior Member level 3
i have problem when i am intialize the value in the entity part...
synthesis and simulation is right ...but real time i got different result from simulation....
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity last is
Port ( a : in std_logic_vector(31 downto 0):=x"FE3A3AB2";
k : in std_logic_vector(31 downto 0):=x"00112233";
clk : in std_logic;
rst : in std_logic;
q: in std_logic_vector(1 downto 0);
d : out std_logic_vector(7 downto 0));
end last;
architecture Behavioral of last is
signal c,d1:std_logic_vector(31 downto 0):=x"00000000";
signal count:integer range 0 to 255:=0;
signal en:std_logic;
begin
process(a,k,c,d1,clk,rst)
begin
if(rst='0') then
d<=x"00";
en<='0';
elsif(clk='1' and clk'event) then
d1<= not(a xnor k );
c(31)<=d1(31);
loop1:for i in 30 downto 0 loop
c(i)<=c(i+1) xor d1(i);
end loop loop1;
case q is
when "00"=> d<=c(31 downto 24);
when "01"=> d<=c(23 downto 16);
when "10"=> d<=c(15 downto 8 );
when "11"=> d<=c(7 downto 0);
when others=> d<=x"00";
end case;
end if;
end process;
end Behavioral;
in the same way i put the value inside the architecture..i got perfect result
ie...
d1<= not(x"FE3A3AB2" xnor x"00112233"); instead of d1<=not(a xnor k);
im using xilinx project navigator 6.3i...
is it software problem........or what else.....
plz its urgent....
Thanks once again hearing from u....
synthesis and simulation is right ...but real time i got different result from simulation....
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity last is
Port ( a : in std_logic_vector(31 downto 0):=x"FE3A3AB2";
k : in std_logic_vector(31 downto 0):=x"00112233";
clk : in std_logic;
rst : in std_logic;
q: in std_logic_vector(1 downto 0);
d : out std_logic_vector(7 downto 0));
end last;
architecture Behavioral of last is
signal c,d1:std_logic_vector(31 downto 0):=x"00000000";
signal count:integer range 0 to 255:=0;
signal en:std_logic;
begin
process(a,k,c,d1,clk,rst)
begin
if(rst='0') then
d<=x"00";
en<='0';
elsif(clk='1' and clk'event) then
d1<= not(a xnor k );
c(31)<=d1(31);
loop1:for i in 30 downto 0 loop
c(i)<=c(i+1) xor d1(i);
end loop loop1;
case q is
when "00"=> d<=c(31 downto 24);
when "01"=> d<=c(23 downto 16);
when "10"=> d<=c(15 downto 8 );
when "11"=> d<=c(7 downto 0);
when others=> d<=x"00";
end case;
end if;
end process;
end Behavioral;
in the same way i put the value inside the architecture..i got perfect result
ie...
d1<= not(x"FE3A3AB2" xnor x"00112233"); instead of d1<=not(a xnor k);
im using xilinx project navigator 6.3i...
is it software problem........or what else.....
plz its urgent....
Thanks once again hearing from u....