Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

intialization in VHDL

Status
Not open for further replies.

amburose

Junior Member level 3
Joined
Jun 21, 2007
Messages
29
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,498
i have problem when i am intialize the value in the entity part...
synthesis and simulation is right ...but real time i got different result from simulation....

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity last is
Port ( a : in std_logic_vector(31 downto 0):=x"FE3A3AB2";
k : in std_logic_vector(31 downto 0):=x"00112233";
clk : in std_logic;
rst : in std_logic;
q: in std_logic_vector(1 downto 0);
d : out std_logic_vector(7 downto 0));
end last;

architecture Behavioral of last is
signal c,d1:std_logic_vector(31 downto 0):=x"00000000";
signal count:integer range 0 to 255:=0;
signal en:std_logic;
begin

process(a,k,c,d1,clk,rst)
begin
if(rst='0') then

d<=x"00";
en<='0';
elsif(clk='1' and clk'event) then
d1<= not(a xnor k );
c(31)<=d1(31);
loop1:for i in 30 downto 0 loop

c(i)<=c(i+1) xor d1(i);

end loop loop1;

case q is
when "00"=> d<=c(31 downto 24);
when "01"=> d<=c(23 downto 16);
when "10"=> d<=c(15 downto 8 );
when "11"=> d<=c(7 downto 0);
when others=> d<=x"00";
end case;
end if;


end process;



end Behavioral;




in the same way i put the value inside the architecture..i got perfect result

ie...

d1<= not(x"FE3A3AB2" xnor x"00112233"); instead of d1<=not(a xnor k);



im using xilinx project navigator 6.3i...
is it software problem........or what else.....
plz its urgent....

Thanks once again hearing from u....
 

nxtech

Full Member level 5
Joined
Jun 13, 2007
Messages
258
Helped
17
Reputation
34
Reaction score
2
Trophy points
1,298
Location
NO HIDDEN LINKS
Activity points
2,772
I hate to say it but it could be the tool. If you can you need to download the newest version of ISE and then try again. Your code looks fine and its not surprising that your actual results are different from your simulation.

The newer versions of the ISE tool have usually fixed limitations of the earlier releases so give that try and let us know how things work out.

E
 

    amburose

    Points: 2
    Helpful Answer Positive Rating

salma ali bakr

Advanced Member level 3
Joined
Jan 27, 2006
Messages
971
Helped
104
Reputation
206
Reaction score
21
Trophy points
1,298
Activity points
7,491
see with the tool first....

then maybe try to put them in both numerical values in a generic then assign them to a and k...or make constants and assign their values to a and k....you can do that since they aren't changed throughout the program
 

amir81

Member level 2
Joined
Mar 1, 2003
Messages
44
Helped
5
Reputation
10
Reaction score
0
Trophy points
1,286
Activity points
322
did ise send you warnings?
 

amburose

Junior Member level 3
Joined
Jun 21, 2007
Messages
29
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,498
No warnings......
the code is here...but i got same problem....

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity last is
Port ( a : in std_logic_vector(31 downto 0);
k : in std_logic_vector(31 downto 0);
clk : in std_logic;
rst : in std_logic;
q: in std_logic_vector(1 downto 0);
d : out std_logic_vector(7 downto 0));
end last;

architecture Behavioral of last is
signal c,d1:std_logic_vector(31 downto 0):=x"00000000";

begin

process(a,k,c,d1,clk,rst)
begin
if(rst='0') then
d<=x"00";

elsif(clk='1' and clk'event) then
d1<= not (a xnor k);--not(x"FE3A3AB2" xnor x"00112233");
c(31)<=d1(31);
loop1:for i in 30 downto 0 loop

c(i)<=c(i+1) xor d1(i);

end loop loop1;

case q is
when "00"=> d<=c(31 downto 24);
when "01"=> d<=c(23 downto 16);
when "10"=> d<=c(15 downto 8 );
when "11"=> d<=c(7 downto 0);
when others=> d<=x"00";
end case;
end if;


end process;



end Behavioral;



but now web update of 6.3i not available......
is it problem...
 

Iouri

Advanced Member level 2
Joined
Aug 17, 2005
Messages
682
Helped
87
Reputation
174
Reaction score
8
Trophy points
1,298
Activity points
4,814
Port ( a : in std_logic_vector(31 downto 0):=x"FE3A3AB2";
k : in std_logic_vector(31 downto 0):=x"00112233";


In "real" world there is no way to initilize inputs like that, you need to apply the real signals, also

signal c,d1:std_logic_vector(31 downto 0):=x"00000000";

will never work you have to use reset signal to initilize those values. For that simple HDL code tool is NOT a problem
 

FvM

Super Moderator
Staff member
Joined
Jan 22, 2008
Messages
49,419
Helped
14,441
Reputation
29,146
Reaction score
13,239
Trophy points
1,393
Location
Bochum, Germany
Activity points
284,388
signal c,d1:std_logic_vector(31 downto 0):=x"00000000";
will never work you have to use reset signal to initilize those values
I don't agree regarding internal signal respectively registers. With most FPGA (for sure with Altera, don't know exactly with Xilinx), registers have a power-on reset state, and it's value is usually inferred from signal initialisation as shown above. It's advisable to have an asychronous reset anyway, but in situations where it isn't available, power-on reset may help.
 

echo47

Advanced Member level 5
Joined
Apr 7, 2002
Messages
3,942
Helped
638
Reputation
1,274
Reaction score
89
Trophy points
1,328
Location
USA
Activity points
33,176
Xilinx also supports HDL initialization of registers in its FPGAs and CPLDs.

I've never needed an asynchronous reset in my Xilinx FPGA projects.
 

robinh

Member level 1
Joined
Jan 18, 2002
Messages
38
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Activity points
254
Signal and port assignment are discarded during the synthesis process. This feature is only destined to simulation and modeling purposes. This is the reason why you get two different results.

The only thing you can give a fixed value during definition is a constant.
 

FvM

Super Moderator
Staff member
Joined
Jan 22, 2008
Messages
49,419
Helped
14,441
Reputation
29,146
Reaction score
13,239
Trophy points
1,393
Location
Bochum, Germany
Activity points
284,388
Signal and port assignment are discarded during the synthesis process.
How do you know? From literature? Believe it or not, FPGA registers have a power-up level that can be utilized in designs. This is surely the case with Altera and, as echo47 confirmed, with Xilinx. I love those expert statements in EDAboard, that aren't founded on any real knowledge.

Port assignments to external ports are actually meaningless in synthesis, assignments to internal ports work in the same way as in simulation, they are valid as default for unconnected ports only.
 

amir81

Member level 2
Joined
Mar 1, 2003
Messages
44
Helped
5
Reputation
10
Reaction score
0
Trophy points
1,286
Activity points
322
as a general rule: initialization of signals (also ports because they are signals) are not synthesizable. neither xilinx nor altera, actel,ql,... support that.
however for some fpgas you can use some attributes ( such as init for xilinx fpgas) to initialize ram or lut.

but remember fpga synthesizers ALWAYS ignore initializations of signals ( try with xst, synplify, leonardo and ... you will get same result). however as far as i know if you want to make an asic you can use signal initialization ( i do not work with asics).
 

vomit

Full Member level 2
Joined
Jun 14, 2002
Messages
148
Helped
14
Reputation
28
Reaction score
4
Trophy points
1,298
Activity points
1,527
amir81 said:
as a general rule: initialization of signals (also ports because they are signals) are not synthesizable. neither xilinx nor @ltera, actel,ql,... support that.

You're right in general. But recently I learned in a Xilinx presentation at our company that their ISE synthesis tool does support initial values. I was rather sceptic, asked it again and got a formal yes.
 

FvM

Super Moderator
Staff member
Joined
Jan 22, 2008
Messages
49,419
Helped
14,441
Reputation
29,146
Reaction score
13,239
Trophy points
1,393
Location
Bochum, Germany
Activity points
284,388
See an example from Quartus handbook with VHDL code of a Register with Reset and High Power-Up Level.
Code:
SIGNAL q : STD_LOGIC := '1'; -- q has a default value of '1'
PROCESS (clk, reset)
  BEGIN
    IF (reset = '1') THEN
      q <= '0';
    ELSIF (rising_edge(clk)) THEN
      q <= d;
    END IF;
  END PROCESS;
So far regarding "neither Altera supports"...

The mechanism behind this code is also explained in Quartus handbook:
Registers in the device core always power up to a low (0) logic level on all Altera devices. However, there are ways to implement logic such that registers behave as if they were powering up to a high (1) logic level.
So the power-up level is actually an option of the synthesis tool, not a harware feature. But is exists and apart from synthesis attributes and such it can be inferred from HDL initilization statements.

I did not claim, that this option exists with all synthesis tools, cause I simply don't know. I assume, that some others tools also offer the option, but probably not all. I may be more difficult for a vendor independant tool. According to the handbook, e. g. Synopsys doesn't support Verilog initial statement.
 

echo47

Advanced Member level 5
Joined
Apr 7, 2002
Messages
3,942
Helped
638
Reputation
1,274
Reaction score
89
Trophy points
1,328
Location
USA
Activity points
33,176
HDL register initialization in Xilinx ISE is described in the XST User Guide chapters "VHDL Language Support" and "Verilog Language Support":
**broken link removed**
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top