(interview)Simplify the circuit with DFF and MUX?

[davyzhu]

Hi all,

How to Simplify the source circuit including the DFF and MUX in the below graph?
The target circuit constraints are (a) minimize the power dissipation (b) the same function with source circuit.

BTW, if change DFF to D-Latch, how to Simplify the circuit?

Any suggestions will be appreciated!
Best regards,
Davy

 

[tarkyss]

input D connects the input D of flip-flop directly
use en signal for gated clock

 

[silencer3]

as long as clock is present at DFF, power dissipation continue. so to reduce power remove clock using EN. For this, (as tarkyss said), connect D to D input of DFF and connect EN to Enable pin of DFF.

if EN input for DFF does not exist, gate the clk using EN signal.

 

[eda_wiz]

tarkyss said it correct. u need to gate the clock.
for this you can use a simple AND gate. or a latch based clock gate circuit(prevents glitches in EN pin getting propagated to CLK of the DFF)

 

[davyzhu]

Hi,

Oh, I see.

I always keep in mind that "don't use gated clock in FPGA". But it seems that it is used in ASIC

Thanks!
Davy

 

[tarkyss]

normally, gated clock will introduce a lot of troubles in ASIC design too, but for power reduction, if you can resolve these problems introduced by gated clock, it is a good choice