Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

interview questions help!

Status
Not open for further replies.

eexuke

Full Member level 4
Joined
Mar 25, 2004
Messages
196
Helped
9
Reputation
18
Reaction score
3
Trophy points
1,298
Activity points
1,934
Dear all,
I met with these interview questions, would you mind help me to answer them? Thanks!
1) What is meant by the term "porosity"? Why is it desirable for a cell or macro to have high porosity?
2) What is an "application-specific memory"? What are some specific examples of this part type?
3) Why is the number of gate inputs to CMOS gates (e.g. NAND or NOR gates) usually limited to four?
 

avimit

Banned
Joined
Nov 16, 2005
Messages
413
Helped
91
Reputation
182
Reaction score
23
Trophy points
1,298
Location
Fleet, UK
Activity points
0
porosity comes form 'porous'. Its basically air gaps in dilectric layers, which reduces the di-electric constant of the layer.

4 or less inputs in a gate: has to do with its input loading. If the input loading is higher, the propagation delay will be high. May be 4 is the sweet spot, and if more inputs are required, then you'd use 2 gates in parallel, and or/mux their outputs.
 

mujju433

Full Member level 3
Joined
Jun 2, 2007
Messages
174
Helped
4
Reputation
8
Reaction score
2
Trophy points
1,298
Activity points
2,293
No actually the number of inputs depend upon the speed like if the inputs are more than 4 then the speed will be low so number of inputs limits speed or u can say fan in limits speed and fanout limits propagation delay...

This is the answer for 3 question

give me some points if my answer is correct

Bye take care

Added after 10 minutes:

The second answer is any memory which is unique is called asic ...it wil be specific for that particular application and the examples are FPGA and CPLD


Correct me if i am wrong

Bye take care
 

avimit

Banned
Joined
Nov 16, 2005
Messages
413
Helped
91
Reputation
182
Reaction score
23
Trophy points
1,298
Location
Fleet, UK
Activity points
0
No actually the number of inputs depend upon the speed like if the inputs are more than 4 then the speed will be low so number of inputs limits speed or u can say fan in limits speed and fanout limits propagation delay...
1. majju433, what is the difference in speed and propagation delay. I reckon these two are the same.

2. If the number of inputs increase, the size of the p-transisor increases very much, and in order to keep the cell height constant, you have to put a limit to number of inputs, or the gate will become very wide.
Also as you increase the number of inputs, the gate becomes a large load due to the number of transisotrs that would have to be driven. So it will cause the driving gate to get slow.
Kr,
Avi
http://www.vlsiip.com
 

forkschgrad

Full Member level 5
Joined
Apr 6, 2007
Messages
271
Helped
18
Reputation
36
Reaction score
8
Trophy points
1,298
Location
Philippines
Activity points
2,363
the answers to your questions can be referred to CMOS IC Layout by Dan Klein.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top