interview question regarding clock skew

[fail1]

Somebody asked me this question in the interview which I couldnt answer:

Say, after CTS your skew is 300ps & you make the clocks fixed .
Now, after detail route the skew gets worse by 300ps.Whta can be the reason?
There are no hotspots or routing congetsion issues in the design.

 

[owen_li]

My comment is about the blockage, even there is no congestion or hotspot.
If two clock tree repowering cells are across a big macro, when after CTS, the timing engine will assume the net are across the macro directly.
But, after routing, the acctual net will detour around the macro to get the next repowering cell. So it will cause some mismatch on the skew. One solution is raising the layer of this clock net, until the net can cross the macro.

so, in a word, layer selection difference between cts and routing will cause the mismatch.

 

[fail1]

Hi,

I am assuming that the repowering cells which you mentioned are the clock buffers cell used by CTS.But if the clock network is fixed, how can that route be detoured after routing...isnt that net across the macro will be a fixed net if its a clock net.

Thanks
Kumar

 

[shelby]

Some of the clock nets may now have SI effects on them.

 

[GI]

Hi fail1,

I agree with owen_li.

The main reason is the difference caused by global routing (not an actual route but an estimate of routing resource allocation) & detail routing. Global routing is used before detailed routing at placement & clock tree stages. And before every routing (global & detail) settings should be adjusted to tell tool the routing rules such as "layer selection", "via usage", "metal widths" (double/triple width), "spacing rules" (double/triple spacing), etc...

According to this, if there is difference between these setting at global & detailed routing steps then there can be mismatches. Also there can be some bugs in tools which may cause this miscorrelation.

Another point is at global routing there is no real extracted data from routings, instead estimated data is used. After detailed routing extracted capacicantes and resistances are used which are more realistic.

I remember myself seeing such discrepancy in Synopsys ICC (IC Compiler) tool 4 years ago (it was related to over-the-macro routing). There were huge memories, which were blocked up to Metal 5 preventing a real detail route to route over the macros. Before detailed routing, global router was not taking into account the memory blockages at Metal 1 to Metal 4, leading to some sort of optimizm.

I hope it's clear,
Best regards,
Gokhan
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