Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Interview question - Need Your opinion

Status
Not open for further replies.

kolla

Newbie level 6
Joined
Jul 31, 2009
Messages
12
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,361
This is an interview question I found and I'm looking for your feedback..
(There was no answer given)

Q: How do you convert transparent D-latch into rising edge D-Flop?

My initial thinking was to simply add a clock to do this.
But maybe the question is asking something deeper??

Would you guys kindly share your thinking ...
 

gck

Full Member level 3
Joined
Oct 17, 2006
Messages
173
Helped
26
Reputation
52
Reaction score
19
Trophy points
1,298
Activity points
2,220
A transperent D-latch already has clock as an input.
The basic difference between D-latch and D-ff is D-latch is level triggered and D-FF is edge sensitive.

So, to make rising edge D-FF, we need two Transperent D-latch, with opposite edge sensitiveness.
 

    kolla

    points: 2
    Helpful Answer Positive Rating

kolla

Newbie level 6
Joined
Jul 31, 2009
Messages
12
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,361
gck said:
A transperent D-latch already has clock as an input.
The basic difference between D-latch and D-ff is D-latch is level triggered and D-FF is edge sensitive.

So, to make rising edge D-FF, we need two Transperent D-latch, with opposite edge sensitiveness.
Thanks gck for the explanation..
Would you show me how the connections should be made..
A drawing or a picture would help a lot..

Added after 55 minutes:

Actually I think I figured it out...
Looks like something like this'd work.
What do u think?

 

gck

Full Member level 3
Joined
Oct 17, 2006
Messages
173
Helped
26
Reputation
52
Reaction score
19
Trophy points
1,298
Activity points
2,220
Yes this connection is correct for Positive edge triggered D-FF.
 

javatea

Newbie level 4
Joined
Dec 6, 2009
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,326
You could think this question in easier way :

DFF are formed by two cascaded latches.
The first one latch is negative-level sensitive.
The second one is positive -level sensitive.
In addition, where does setup-time and hold-time come from?
For setup time, it is the amount for capturing value in the first latch.
For hold time, it is the amount for value come out in output of the second latch.

For your reference
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top