interview question.combinational circuit frequency division

[vlsi_maniac]

1)Design a simple circuit based on combinational logic to double the output frequency
2)Design a COMBINATIONAL circuit that can divide the clock frequency by 2.

thanks

 

[senthilos]

Re: interview question.combinational circuit frequency divis

1) Double clock frequency.
An EXOR gate with one input being the original clock signal. The other input is the clock delayed by cycle_time/4. The delay can be achieved by buffers. The output is now double the clock frequency.

2) Divide the clock frequency by 2
A 2:1 MUX with CLK as select signal. The 0 select input is just the output. The 1 select input is output_bar(NOT output).

Hope this helps.

 

[harikrishnah]

Re:combinational circuit frequency division

Take an xor gate connect output to the one of the input of the same. give clk signal as the 2nd input. the verilog code for the same is given below
module hari (input in,rst,output reg ot);
always @(in or rst)
begin
if(rst)
ot<=0;

else
ot<=ot ^ in;
end

endmodule