interview preparation for design engineer in vlsi

[Mkanimozhi]

interview preparation

Hi,
anyone help for interview preparation, wat all are the area's i have to go through, and wat they ask for design engineer in vlsi, wat rae the subjects i have to cover.

regards
kanimozhi

 

[anoop12]

Re: interview preparation

Hi,
BASICS!!
This is the point you have to be strong at. Go through
0) HDLS (Strong design/verif skills)
1) FPGA Design flow (Flow chart).
2) Definations like Synthesis, CPLD, FPGA, P n R......
3) Tools that you have used.(Versions)
4) Projects that you have carried out. Very important
5) CMOS knowledge ( Basic)
6) (Power, AreA, Speed, Cost ) in FPGA lifecycle.

These some of the important points

 

[mrngorickets]

Re: interview preparation

Hi,

Thanks very much for this comment. It help me to think about my ideals.

Tks again and pls keep posting.

 

[Alexium]

Re: interview preparation

Hi,
BASICS!!
This is the point you have to be strong at. Go through
0) HDLS (Strong design/verif skills)
1) FPGA Design flow (Flow chart).
2) Definations like Synthesis, CPLD, FPGA, P n R......
3) Tools that you have used.(Versions)
4) Projects that you have carried out. Very important
5) CMOS knowledge ( Basic)
6) (Power, AreA, Speed, Cost ) in FPGA lifecycle.

These some of the important points

Thank you!

 

[mrngorickets]

Re: interview preparation

Hi,
anyone help for interview preparation, wat all are the area's i have to go through, and wat they ask for design engineer in vlsi, wat rae the subjects i have to cover.

regards
kanimozhi

If you want to get more materials that related to this topic, you can visit: **broken link removed**

Best regards.

 

[sanju_]

Re: interview preparation

hi
Verilog Questions
Digital Questions
VERILOG FAQ GENERAL refer this links once will be better...
Sequential Circuits Part-IV

 

[tua022012]

Thanks for your link. It's useful for our community.
Same material can be found at: **broken link removed**
I hope it's useful for you and you like it. Please continue sharing more information at this topic.
Best rgs!

 

[sakthikumaran87]

you can also read the difference between synthesizable and non-synthesizable code, lint tools basics and use, clock domain crossing basics, FIFO, FSMs etc.

 

[mrflibble]

Speaking of lint tool basic use, what are good linting tools for verilog?

 

[sakthikumaran87]

Spyglass, Leda