# interrupt problem in 16f676

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#### Noman Yousaf

##### Full Member level 4
hi

i am using 16f676 with assembly language. i want to make PWM based lamp dimmer.
for this purpose, i have to use 2 interrupts. external int and timer 1 interrupt.
can i use both? when external interrupt will wake, timer1 will start, make a port hi. when it will turns off by overflowing, will make the port low. and will wait next external interrupt.
please confirm can it be possible?

if yes then please tell me the origins setting for both ISRs.

#### Aussie Susan

That chip has its interrupt vector at 0x0004 - check Figure 2-1 in the data sheet.
As there is only 1 interrupt vector, you will need to check for yourself which interrupt source has triggered. In C this is done by codew such as
Code:
if( _TMR1IE && _TMR1IR)
{  ... }
if( _INTE && _INTF)
{ ... }
(The above is made up but demonstrates the point)
Of course you need to clear the appropriate IF bit once you have worked out the source.
Susan

#### Noman Yousaf

##### Full Member level 4
i use assembly. please write assembly code

- - - Updated - - -

can both interrupts be used at once?

#### swapan

##### Full Member level 4
Yes, multiple ISR could be used.

See the following code.

Code:
org		0X0004
int_serv
movwf   	w_temp              ; Save W
swapf   	status,w
movwf   	s_temp             	 ; Save STATUS
bcf		status,rp0
btfss		intcon,1		; See if external interrupt occurred.
goto		tmr1_int		; Otherwise attend TMR1 interrupt.
clrf		tmr1h		; Clear TMR1
clrf		tmr1l
bsf		pie1,0		; Enable TMR1 interrupt.
bsf		XXXXXX    	; Set the bit of your interest high.
bcf		intcon,4		; Disable external interrupt.
bcf		intcon,1		; Clear external interrupt flag.
goto		end_int

Tmr1_int:
bcf		XXXXXX	; Set the bit of your interest low.
bcf		pir1,0	; Clear MR1 interrupt flag.
bcf  		pie1,0	; Disable TMR1 interrupt.
bsf		intcon,4		; Enable external interrupt.
end_int
swapf		s_temp,w
movwf		status
swapf		w_temp,f
swapf		w_temp,w
retfie

#### Aussie Susan

Be careful with the above code - it only checks for the interrupt flag being set which can lead to problems.
If you look at the structure of the code I suggest, you should first check that the interrupt enable bit is set and then for the interrupt flag. Only if BOTH are set should you process the interrupt.
For example, you might have an external interrupt which means that you have no idea what will trigger it and when that trigger might occur. It may even occur when you have disabled the external interrupt processing by the hardware (i.e. the interrupt enable bit is clear).
Then the timer interrupt occurs and the ISR is called which can handle both the timer and the external interrupt. Without testing for the interrupt enable bit, you could incorrectly and inappropriately try to process the external interrupt.
Susan

#### swapan

##### Full Member level 4
Be careful with the above code - it only checks for the interrupt flag being set which can lead to problems.
If you look at the structure of the code I suggest, you should first check that the interrupt enable bit is set and then for the interrupt flag. Only if BOTH are set should you process the interrupt.
For example, you might have an external interrupt which means that you have no idea what will trigger it and when that trigger might occur. It may even occur when you have disabled the external interrupt processing by the hardware (i.e. the interrupt enable bit is clear).
Then the timer interrupt occurs and the ISR is called which can handle both the timer and the external interrupt. Without testing for the interrupt enable bit, you could incorrectly and inappropriately try to process the external interrupt.
Susan

This is a mere hint, not the entire code. It is assumed that rest could be devised by anybody with minimum experience. Had the guy provided schematic, complete could've been given.

#### Aussie Susan

swapan - I accept your comment and that the code was an example only (as was my pseudo-code).
However the fact remains that the ISR must check for the 'interrupt enable' bit being set if it is to stop false activation of the appropriate code segment within the ISR.
This situation is a very real problem with devices that share an interrupt vector.
Susan

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