staraimm
Full Member level 2
Did everyone met the situation:
I used the Spartan-3 FPGA chip and PIPE core from xilinx company to realize my project. In the design, I wrote a interrupt controller according to the PIPE logic core documentation.
The fact is that if the interrupt request frequency is low, the interrupt controller can work well. But if the frequency is very high, it seems that the CPU can't receive the interrupt from the interrupt controller.
I think the controller is dead.
Does anybody give me any suggestion?
I used the Spartan-3 FPGA chip and PIPE core from xilinx company to realize my project. In the design, I wrote a interrupt controller according to the PIPE logic core documentation.
The fact is that if the interrupt request frequency is low, the interrupt controller can work well. But if the frequency is very high, it seems that the CPU can't receive the interrupt from the interrupt controller.
I think the controller is dead.
Does anybody give me any suggestion?
