Interrupt line of the PCI bus from the bus

[bizoo]

Feeding the Interrupt line of the PCI bus from the motherboard to another device

HI all,
I am basically a software engineer who had a small circuit design issue and need some guidance.

I need to take the interrupt line of the PCI card from my motherboard and feed into a small FPGA which has a dedicated input connector.

I have measured the signal on the PCI interrupt and its active low and pulled up to 5V with pull up registers when no activity is on the line . The FPGA input signal requirement is 3.3 Volts.
Now from my limited knowledge of electronics, i can remember that for dividing the voltage i need a couple of resistors with the right ratio.

But the FPGA is an expensive one and i do not want to blow anything up. I am not sure about the role of pull up resistors and how the active low logic will affect my input to the FPGA.

Pretty trivial question for some but as i said, i am a software enginner and had my last interaction with hardware design some 6 years ago in University.
Any help will be appreciated!

cheers!

 

[cks3976]

Weak Pull-up / Pull-down is pulling the signal High/Low to VDD/GND when there are no actual transitions are happening on that signal.

Weak PU/PD will make sure that any glitch on that signal will not drive the end device (FPGA in this case) to an incorrect logic.

For a correct PU, one should ensure that the Pull-high should be to a voltage that is equal to the operating voltage of the target device (FPGA in this case). So as you have correctly pointed out, pulling a signal to 5V and connecting that signal to the 3.3V I/O of FPGA might definitely cause damage to the device.

BTW... when I mention Weak PU/PD, it is connecting the signal to VDD/GND through a very high value resistor (in the range of 4.7K Ohm to 10 K Ohm)..

 

[bizoo]

HI!
Thanks for the reply!

but here is another thing what i was thinking (could be wrong here though so pardon my ignorance)

One end of my wire is connected to the PCI INTR pin on the PCI slot. the second end is being fed into the FPGA board.

Now what i do not know is where is the PU resistor located. Assuming that PU resistor is actually on the motherboard near the PCI controller , in this case, i am just connecting INTR pin of the PCI card to my FPGA board directly regardless of the PU resistor.

In this case, i do not have to worry at all about the size of the PU resistor.

So assuming that PU resistor is on the motherboard, am i making any sense?

I hope what i said above make sense!
Thanking in anticipation!

cheers!

 

[cks3976]

Normal practice is to have the weak PU/PD near the load. In this case the FPGA. It is a better idea to actually inspect whether or not a PU has been added near the driver (PCI Controller).

Measure the voltage on interrupt pin when Interrupt is asserted and when not asserted. PCI interrupt is an Active low signal. So when the interrupt is asserted, you should get Zero reading on your multimeter. Check carefully what the meter reads when the Interrupt is not asserted. If this is 5V, then that means there could be a Weak pull-up near the PCI controller- for 5V. Even in that case you would need to convert the signal to 3.3V level using a a voltage translator (something like TI- Voltage Level Translation - Dual Supply Translator - SN74LVC1T45 - TI.com).

 

[bizoo]

Hi!
thanks again for the insightful reply.

i just took the measurements and indeed active low and levels are 0 and 5 volts. So somewhere on the motherboard is a PU resistor.

Also i looked into the PCI standard and found out that the interrupt line is open drain.
So the whole issue boils down to converting a 5V open drain pulled up signal to 3.3 Volts for the FPGA board.

Additionally timing is another issue. Interrupts are really fast and they are dealt with quickly too and any voltage conversion from 5->3.3 should not affect the slew rate of the original PCI signal.

Can You please suggest some thing for that?
cheers!

 

[cks3976]

Check the link I have given. That suggests some voltage translators from TI. Don't worry about the additional delay that will be added by the translator that will be minimal.