Interpreting I/O parameters

[s_cihan_tek]

as-i parameter

Hi all,

I'm trying to use a 74lvc4245 level shifter to shift the voltage levels of the 8bit data lines between a 3.3V FPGA (max ii) and a 5V LCD. I wasn't able to decide if current limiting resistors or something else is needed in these connections below:

1- Connection btw. the FPGA and the level shifter
2- Connection btw. the level shifter and the LCD

And here are the related datasheets and page numbers of the related specs.

FPGA at pages ..74..
74lvc4245
There isn't any info about i/o currents in the LCD datasheet so i'm not giving its url here.

I would really appretiate if someone could show me how to interprete these I/O parameters when connecting the i/o pins of these IC's together.

Regards...

 

[Audioguru]

Input Low Current

Its output is going low so it is sinking. It can't be a logic low if the load current is more than 4mA.

 

[Kral]

Re: Input Low Current

KoRGeNeRaL,
Audioguru is correct. Iol is the maximum current that the device can sink while still maintaining a specified value of Vol.
.
If the device is sourcing Iol, then Iol is the maximum current that the device can source while maintaining a specified Voh.
Regards,
Kral
Regards,
Kral

 

[s_cihan_tek]

Re: Input Low Current

Thanks for the replies. I read my question again and figured out that i mistyped my question.

I'm going to ask a new question to understand this I/O current limiting stuff more clearly by using specific ICs.

Please look at my first message again to see my new question.

 

[Kral]

As I understand the 74LVC4245A data sheet, port A is the 5V Port. Since the LCD is a 5V device it would be connected to port A. The FPGA would be connected to port B which is the 3V port. You do not need to use current limiting resistors. Both the input and output voltages of the 4245 will be compatible with the devices to which they are connected The FPGA input input leakage current is only 10uA which will not be a problem for the 4245. I'm assuming that the LCD device can also handle 10uA on its output pins.
Regards,
Kral

 

[s_cihan_tek]

Thanks for the reply.

As far as i understand from your last post, unless applied voltages doesn't exceed the recommended values of an input, or in other words, the voltage levels are compabitle, a current limiting resistor is unnecessary. Is that right? Or thats only true for CMOS inputs?

One more thing. I know that CMOS inputs sink very low amount of current at steady state, but they need a significant amount of current initially for charging their input capacitance. How can i make sure that the initial current requirement of this charging capacitor don't damage the output of my IC by exceeding its max. output current rating?

 

[Kral]

KoRGeNeRaL,
You are correct regarding current limiting resistors. As long as the voltage levels are compatible, there is no need for current limiting resistors. This is true regardless of whether CMOS is used or not.
.
As far as your concern about exceeding the output current capacity of the FPGA, there are two concerns:
1 The effect of capacitance on the rise and fall times
2 The effect of capacitance on the power dissipated in the output drivingt transistors in the FPGA. This can be estimated by the equation P = C (Vcc)^2 f (for each output). I doubt that this dissipation will be contribute a significant amount to the total device dissipation. I would follow the following links from the data sheet for more information:
.
Understanding and Evaluating Power in MAX II Devices
PowerPlay Power Analysis
.
Regards,
Kral