ebuddy
Full Member level 3
Hi,
I have a design, in which there is a hard macro memory IP block. The data bus of the memory is a tri-statable bus. When the memory goes idle, the bus goes high impedance. To prevent the floating net from causing any power leakage issue to other gates, I did a design like the one in the attach diagram.
Basically the NAND gates allow data bus to drive the rest of the logic when and only when EN is high; when EN is low, NAND gate will ignore the voltage level of the floating net, thus effectively block the high impedance from spreading to the rest of the logic.
You guys see any problem with this implementation vs. other methods (weak pull-up/down, bus latch)? Thanks.
ebuddy
I have a design, in which there is a hard macro memory IP block. The data bus of the memory is a tri-statable bus. When the memory goes idle, the bus goes high impedance. To prevent the floating net from causing any power leakage issue to other gates, I did a design like the one in the attach diagram.
Basically the NAND gates allow data bus to drive the rest of the logic when and only when EN is high; when EN is low, NAND gate will ignore the voltage level of the floating net, thus effectively block the high impedance from spreading to the rest of the logic.
You guys see any problem with this implementation vs. other methods (weak pull-up/down, bus latch)? Thanks.
ebuddy
![CropperCapture[12].jpg](/data/attachments/4/4015-f294ec8b53995133243ff591c9c8f26f.jpg)
