internal pulled up resistor described in HDL

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shaiko

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Is it possible to inffer internal pull-up (or pull-down) resistors in HDL (without doing it in the synthesis tool) ?
 

yes it is possible in the case of mixed signal modelling.by using either Averiog or AMSvhdl language but for these things we need simulators which supports analog and mixed signal hdl.we cant run this using either xilinx or quartus ise..
 
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    shaiko

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So it's impossible to do with synthesizable VHDL/Verilog ?
 

It is not clear what you want to do. Where is the pull-up in the final circuit?
 

On the I/O pin of the FPGA...
 

Yes. That's what I'm looking for. I know about the tool options.
I was asking about doing the same using purely HDL...
 

The altera coding guide makes no mention of infering pull-ups from code. So you will have to do it the "normal" way. Create settings that make the default whatever and the individual pin exceptions osmething else.
 
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