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I guess, the problem is not particularly in interfacing rather than configuring the MAC, configuring the PHY, providing an IP (possibly also UDP or TCP) network stack. If so, the question can't be answered in a brief. Usual FPGA ethernet communication solutions are performing most of the said tasks through a software processor as Xilinx MicroBlaze or Altera Nios II. A pure hardware solution would be basically possible but involve a lot of configuration and management functions to be implemented in HDL.
dear friends,
I want to know the minimum MAC configuration for interfacing with FPGA?
can anyone help me?
does anyone have sample code example for this?
I believe you will need to start thinking out the box. A minimal MAC will have at least an interface to your PHY device (in your case LAN91C111, but of course there are others).
Then you will need to handle the datastream coming in, and (most probably) put some storage device (FIFO) in the datastream so that the upper layers have time to take care of the different protocols.
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