Interfacing DVI to an FPGA ?

[shaiko]

Hello,

Does Altera / Xilinx FPGA's have IO ports that can support direct connectivity with DVI ?

 

[Dan Mills]

IIRC DVI is LVDS with a few 5V cmos lines for things like EDID data, so yes (mostly) but you will need to level shift the I2C if you want access to the EDID.

You will need to pick a part with sufficient high speed serdes and transceivers if you want to run at much above minimum rate, and will need some glue of transient/EMC and dc bias.
Pretty much anything with the high speed trancevers should have sufficient PLL resources for this.

Regards, Dan.

 

[shaiko]

So the data and clock lines are plain LVDS ?
If so, why would anyone require a device like this:
**broken link removed**
?

 

[aruipksni]

So the data and clock lines are plain LVDS ?
If so, why would anyone require a device like this:
**broken link removed**
?

no in DVI and HDMI they are using TMDS signaling.

 

[Dan Mills]

I thought TMDS was a protocol thing (A form of 8b10 coding) rather then being an electrical standard thing, but I turns out I was wrong about the electrical standard in use, it is actually CML, which most FPGAs can also do, so no real problem there.

Regards, Dan.

 

[shaiko]

This is what I know:
TMDS in a protocol that defines both the electrical levels and the encoding scheme.

My question is:
What is the electrical standard?
Both Dan & Wikipedia mention CML.

But this document doesn't:
**broken link removed**

 

[FvM]

Yes, it's not CML (differential current driven with ground referred termination), it's current driven with 3.3V referred termination.

It's no big thing to make a level shifter that interfaces TDMS level to a FPGA supported differential standard. If it makes sense to do the TDMS decoding in FPGA is a different question.

 

[shaiko]

If it makes sense to do the TDMS decoding in FPGA is a different question.

So, you're suggesting to do both the level shifting and the TMDS decoding on an external IC ?

 

[std_match]

I think HDMI is equivalent to the digital part of DVI. The Digilent Atlys board has both HDMI input and output, and uses the TMDS141 chip from TI.
You can find the schematis here:
http://www.digilentinc.com/Data/Products/ATLYS/Atlys_C2_sch.pdf

 

[shaiko]

If I understand correctly - TMDS defines both the electrical levels and the 8 to 10 bit encoding scheme.
The electrical interface is named DVI.

This application note states that all Xilinx FPGAs from Spartan 3A and above feature DVI compliant IOs:
https://www.xilinx.com/support/documentation/application_notes/xapp460.pdf

Going to Altera and looking at the brand new Aria 10...
https://www.altera.com/en_US/pdfs/literature/hb/arria-10/a10_handbook.pdf
Searched the words TMDS & DVI - nothing found.

What do you think?

 

[shaiko]

std_match,
Please look at the PMODA connector.
This one has traces directly leading to the FPGA.

 

[FvM]

Xilinx Spartan 3 and Spartan 6 has differential IOs with a common range supporting TDMS on some banks, they can receive DVI without separate level shifters.