vlsi_whiz
Full Member level 4
pci9056 bg
My project requires interfacing the BlackFin 561 DSP processor with the PLX PCI 9056 PCI I/O accelerator. The 9056 is setup in the C Mode. Has anyone done this type of interfacing. Suggestions/ideas are most welcome.
I've read the App notes bout interfacing the 9054 to TI DSP processors in the C modes and have got some ideas. What i need to know is when the 9056 is configured in the slave mode..how to interface it with BF561 bus? In the master mode, the PCI9056 will issue a Bus request via the LHOLD pin which has to be routed to the BR# of the BF561. The BG# of BF to the LHOLDA of 9056. How will the BF initiate a transaction on the DSP bus?
Thx
My project requires interfacing the BlackFin 561 DSP processor with the PLX PCI 9056 PCI I/O accelerator. The 9056 is setup in the C Mode. Has anyone done this type of interfacing. Suggestions/ideas are most welcome.
I've read the App notes bout interfacing the 9054 to TI DSP processors in the C modes and have got some ideas. What i need to know is when the 9056 is configured in the slave mode..how to interface it with BF561 bus? In the master mode, the PCI9056 will issue a Bus request via the LHOLD pin which has to be routed to the BR# of the BF561. The BG# of BF to the LHOLDA of 9056. How will the BF initiate a transaction on the DSP bus?
Thx
