mrflibble
Advanced Member level 5
" the receive code is called, and if sw1==0 the async_transmitter code is called !!!! "
Yes, I guessed this might have been your Software Land induced fantasy. But in Hardware Country it doesn't work like that. The best advice here is to actually think how the hardware should look. After all, verilog is a Hardware Desciption Language.
Besides ... doesn't the fpga4fun site have a complete module in it already with transmit + receive? I recall from back then just taking the code, and simply plonking it in and it works. All I had to adjust was the bitrate.
---------- Post added at 00:28 ---------- Previous post was at 00:25 ----------
besides ... waitaminute. You said you already had it working for 1 fpga to PC using hyperterminal right? So why this curious construction?
For each fpga you will have both the RX + TX modules in there. So first do 1 fpga that has both RX + TX, and hook that up to PC with hyperterminal. Then you can send data between fpga and pc in both directions. Once you got that working simply duplicate it and put it in 2nd fpga.
Yes, I guessed this might have been your Software Land induced fantasy. But in Hardware Country it doesn't work like that. The best advice here is to actually think how the hardware should look. After all, verilog is a Hardware Desciption Language.
Besides ... doesn't the fpga4fun site have a complete module in it already with transmit + receive? I recall from back then just taking the code, and simply plonking it in and it works. All I had to adjust was the bitrate.
---------- Post added at 00:28 ---------- Previous post was at 00:25 ----------
besides ... waitaminute. You said you already had it working for 1 fpga to PC using hyperterminal right? So why this curious construction?
For each fpga you will have both the RX + TX modules in there. So first do 1 fpga that has both RX + TX, and hook that up to PC with hyperterminal. Then you can send data between fpga and pc in both directions. Once you got that working simply duplicate it and put it in 2nd fpga.