sebas
Junior Member level 2
Hi,
I have a design in which I use multiple cores for connecting to different interfaces: SPI, I2C, UART, etc. Each interface outputs the data to memory. I want to be able to both transmit data from the interface cores, read data from them and configure them (baud rate for example for UART). How can I do this? Can I use the Wishbone bus and build a master core to drive the operations, the interface cores being the slaves? Is it much easier if don't use the Wishbone and just build my own interconnections bus?
Basically my question is how do large design connect cores, do they all use a microprocessor? Looks like it by what I see on Xilinx' website, for example.
Thanks
I have a design in which I use multiple cores for connecting to different interfaces: SPI, I2C, UART, etc. Each interface outputs the data to memory. I want to be able to both transmit data from the interface cores, read data from them and configure them (baud rate for example for UART). How can I do this? Can I use the Wishbone bus and build a master core to drive the operations, the interface cores being the slaves? Is it much easier if don't use the Wishbone and just build my own interconnections bus?
Basically my question is how do large design connect cores, do they all use a microprocessor? Looks like it by what I see on Xilinx' website, for example.
Thanks