Intel FPGA input voltage maintained between Vil and Vih : what's happening?

[zian]

Hi,
Considering these settings :

• Cyclone 10 LP (or Cyclone II / Cyclone III / Cyclone IV)
• IO configured as Input LVTTL 3.3V (Vilmax=0.8V Vihmin=1.7V)
• Voltage maintained between 0.8V and 1.7V on this input (between 0V and 3.3V in fact)
• No CLK rising edge on the D-register on this IO signal during this period of voltage between 0.8V and 1.7V (elsewise a metastability will occur, than can be stopped with a double D-register, but will occur each time, so it may damage the input over the long-term ?)
• Weak Pull-up and/or clamp can be set or not (with normally no influence)

Has somebody ever try this ? Without CLK rising edge it's normally possible without damaging the FPGA over the long-term ?

Thx

 

[FvM]

The input buffer may have increased power dissipation, but not dangerous for the device. Of course the input level is undefined. There are in fact many cases where in or inout ports are driven with level between Vl and Vh for extended periods, e.g. tri state busses. You can use IO features like schmitt trigger or bus hold to enforce a valid input level.

 

[zian]

Thanks for your answer.
For the tri-state mode, I use the IO weak pull-up of the Cyclone 10LP to avoid undefined voltage.
Unfortunately there is no schmitt trigger possibility with IO on Cyclone 10LP.
Bus hold is possible, I've never used it, thanks for this idea, it may solve my problem !
Because the real matter is that there is an AND gate directly connected to input on the IO schematics presented on the Cyclone 10LP datasheet. This AND gate should be designed to deal with voltage between Vilmax and Vihmin (I think it's not possible with a classic AND gate), but it's obvioulsy not written in the Cyclone 10LP datasheet.

 

[FvM]

Why do you think to have a problem? Worst case you get slightly increased current consumption of the input buffer and high frequency oscillations if the input voltage strikes the threshold level. The FPGA will still work and not be damaged.

This AND gate should be designed to deal with voltage between Vilmax and Vihmin (I think it's not possible with a classic AND gate), but it's obvioulsy not written in the Cyclone 10LP datasheet.

It's not possible at all with digital input ports.

--- Updated Aug 15, 2021 ---

What's the speed and source impedance of the signal driving the pin?

 

[zian]

>> What's the speed and source impedance of the signal driving the pin?
Speed : quite slow (analog signal connected also on an ADC) / but it can also be a digital signal TTL (that's why it's connected on an FPGA input)
Source impedance : very low (it can be a little power supply), so now I know that I can't use the bus hold
Voltage : between 0 and 3.3V

Here is the IO schematics of a Cyclone 10 LP with my annotations (in red), showing the "AND Gate".
I suppose that it's not a classic "AND gate" but just one schematic of a more complex one, accepting voltage between Vilmax and Vihmin.

Concerning the threshold of the FPGA input, it's the threshold of the D-Register. I think if no CLK rising edge is applied, there will be no oscillation because oscillations would be on the Q pin with a CLK rising edge.
Moreover, I think there is not really a threshold between Vilmax and Vihmin because there is no schmitt trigger ?

Here is a D-Register high-level schematic :

So there are also a NAND Gate and an Inversor to deal with ...

So here is a NAND Gate with MOS :

My issue is finally : if the Vgs are not 0 or 3.3 (so between Vilmax and Vihmin), the Rdson will be not close to 0 and not high impedance, so that the Push-Pull output can be undefined and oscillate.
My only hope is that with no CLK rising edge, all is working fine without bad cases.
I mean : if CLK is the B input of NAND gate, and CLK is always 0, bottom part is always HZ and up part is always Vcc, and no matter with the 2 MOS connected to the input A with RDson between 0ohm and HZ (150 ohm for example, depending from Vinput between Vilmax and Vihmin)

 

[FvM]

Seriously I don't inderstand your concerns. If the input level is between Vl and Vh, its logic state is undefined and can be read either 0 or 1 by the FPGA fabric. In practice, if you apply a slowly varying voltage to the input, you'll observe an individual threshold of each input. Near this threshold, the logic state will arbitrarily jump and possibly oscillate. No problem as no defined logic state can be expected for the applied input voltage.

If you are reading the input in your FPGA logic, consider that an asynchrounous signal must be synchronized to the FPGA clock, after the synchronizer chain you'll obtain a defined 0 or 1 signal even if the input level is between Vl and Vh.

So what's the problem altogether?

 

[zian]

The problem is when High side and Low side MOS are working together with rdson(high) + rdson(low) = 300ohms (for example) at one moment :
3.3 / 300 = 11mA
Normally it's only during transitions : that's why FPGA are working with peaks currents each CLK rising edge.
If one input is for example fixed at 3.3/2=1.65V (possible in my case), it creates this 11mA consumption, not only during transition, but all the time.
If 16 inputs are doing this (in my case), it's 176mA.
And 11mA is an example, it can be more and damage the FPGA input over long term period.

Now with my last answer, I'm sure that due to CLK connected to the 2 NAND in D-register, these cases are not possible. (The AND gate can also have undefined output : no influence)
It was not obvious before this mini technical study (not exhautive, but ok to solve my litlle worry)

 

[zian]

If the input level is between Vl and Vh, its logic state is undefined and can be read either 0 or 1 by the FPGA fabric. In practice, if you apply a slowly varying voltage to the input, you'll observe an individual threshold of each input. Near this threshold, the logic state will arbitrarily jump and possibly oscillate. No problem as no defined logic state can be expected for the applied input voltage.

I will not have this problem of oscillation beacause I will not apply CLK rising edge when my inputs will be in "analog mode".
In digital mode, this potential problem during transitions is easy to solve with 2 D-register (solution for metastability).
Concerning the individual threshold, it's not working like that, it's not a schmitt trigger, there is no threshold value, it's more like an analog conversion from input to output (easy to see with the NAND schematic, and the Vgs applied).

 

[FvM]

The specific of a ST gate is that it has hysteresis, threshold of a digital gate is simply the voltage where output changes between high and low.

I see that you are mostly guessing about Cyclone 10 input stage and actual behaviour, e.g. expectable worst case current consumption with CMOS gate input in midrange, risk to damage the device. No need for further comments.

 

[zian]

Really sorry, I think I have to add that most of gates don't have hysteresis and threshold which is "simply the voltage where output changes between high and low".
Schmitt Triggers, hysteresis and threshold are luxurious things and are not available with almost all inputs of FPGA .
I'd really have prefered that FPGA inputs works like this with threshold or hysteresis :'(
Maybe in the future, but I think it's too expensive because FPGA have too much IO...

 

[std_match]

I don't think you have a problem, but you can probably use the "bus hold" function to create a Schmitt trigger input by adding a series resistor. This will increase the source impedance, and the maximum signal frequency will be limited.

 

[KlausST]

Hi,

generally the situation of floating innput voltage or static input voltage between true HIGH and true LOW should be avoided.
This can be done by:
* external totoem pole drivers
* external pull up, pull down or bus keeper
* internal pull up, pull down or bus keeper
It should be rather simple to choose one of the above solutions.

What can happen:
* increased static supply current
* oscillation --> high EMI, high current
* metastability at input FF. (This does not mean it will happen)

Klaus

 

[zian]

I don't think you have a problem, but you can probably use the "bus hold" function to create a Schmitt trigger input by adding a series resistor. This will increase the source impedance, and the maximum signal frequency will be limited.

Excellent idea !
In my case, I will not need it because I've just not to do rising edge of CLK when the input signal its in the forbidden zone.
But in other situations, your idea seems great, I will simulate it to be sure it's working well.
EDIT : I never used Bus-Hold because I didn't find any application to need it, with this solution, it's for example possible to work with signal with slow rising edge, I'm very happy to learn it today, thx again

What can happen:
* metastability at input FF. (This does not mean it will happen)

Yes, it's exactly the last matter to deal with.
So if I don't apply rising edge of CLK with the IO FlipFlop, there will be no metastability, and everything will be ok.
And it's possible because I know when the mode is "analog" with forbidden zone on this IO, and when the mode is "digital" with Vih and Vil respected.

Metastability can be a nightmare on a system when it occurs from time to time. Asynchronous inputs always need 2 FF to avoid this, so that metastability stays between these 2 FF.

 

[std_match]

In my case, I will not need it because I've just not to do rising edge of CLK when the input signal its in the forbidden zone.
But in other situations, your idea seems great, I will simulate it to be sure it's working well.

The increased current in the input stage and the "bus hold" function are not related to CLK, they are both valid even without an edge on CLK.

 

[KlausST]

Hi,

Yes, it's exactly the last matter to deal with.
So if I don't apply rising edge of CLK with the IO FlipFlop, there will be no metastability, and everything will be ok.
And it's possible because I know when the mode is "analog" with forbidden zone on this IO, and when the mode is "digital" with Vih and Vil respected.

Metastability can be a nightmare on a system when it occurs from time to time. Asynchronous inputs always need 2 FF to avoid this, so that metastability stays between these 2 FF.

I know what you mean, but I can´t fully agree.
Metastability may occur. Yes, but what´s the "real" problem with metastability: It´s a unknown and unpredictable FF output state.
But with the invalid input voltage, you already have an unpredictable and unknown input state.
So with or without metastability: you have an unknown and unpredictable FF output.

So again my recommendation: Avoid invalid input voltage levels. This is simple and as already mentioned needs no (or low) hardware effort (when using the internal bus keeper or internal pull up) and you get rid of the problems.

Klaus

 

[zian]

I know what you mean, but I can´t fully agree.
Metastability may occur. Yes, but what´s the "real" problem with metastability: It´s a unknown and unpredictable FF output state.
But with the invalid input voltage, you already have an unpredictable and unknown input state.
So with or without metastability: you have an unknown and unpredictable FF output.

So again my recommendation: Avoid invalid input voltage levels. This is simple and as already mentioned needs no (or low) hardware effort (when using the internal bus keeper or internal pull up) and you get rid of the problems.

I agree with that, but I can't avoid this forbidden zone in my design, because it's also connected to an ADC, and add a MUX is impossible : due to size and price.
As I saied my chance is that the FF output will be not be in a metastability state until I activate a CLK rising edge, and I will not do it with the forbidden zone on input. So normally it's OK.

--- Updated Aug 17, 2021 ---

The increased current in the input stage and the "bus hold" function are not related to CLK, they are both valid even without an edge on CLK.

True. Without edge of CLK, I avoid metastability on the first FF output, and I avoid more increased current too.

 

[FvM]

Some wrong assumptions. Increased current consumption and possible oscillations for "analog" input level range will already occur in input buffer (located in the retctangle "Input Pin ... Delay") and don't depend on operating the input register.

 

[zian]

Some wrong assumptions. Increased current consumption and possible oscillations for "analog" input level range will already occur in input buffer (located in the retctangle "Input Pin ... Delay") and don't depend on operating the input register.

Yes, that's one thing interesting :
- I ever used the "rectangle output delay" with adding a delay (in the .sdc file exactly with Intel/Altera), I remember it was adding a delay or not, and it was not possible to choose the delay with precision : but it was possible to know its value with the timing file after routing.
- But I never used something related to the "rectangle Input pin to ... delay", but I think it can be something equivalent to the rectangle output delay ? It's something else ?
- So why do you think there will be "Increased current consumption and possible oscillations for analog input level range will already occur in input buffer" ? I'm interested with your assumption : I didn't think to this part of the IO block.

Anyway, I will try experiment on 10 inputs with varying (in the same time) inputs values from 0.8V to 1.7V, and measuring the Vccio main current (with Vccio = 3.3V).

 

[FvM]

Anyway, I will try experiment on 10 inputs with varying (in the same time) inputs values from 0.8V to 1.7V, and measuring the Vccio main current (with Vccio = 3.3V).

Good idea.

- So why do you think there will be "Increased current consumption and possible oscillations for analog input level range will already occur in input buffer" ? I'm interested with your assumption : I didn't think to this part of the IO block.

Simply consider that FPGA inputs have either a single configurable input stage or multiple input stages for different IO standards (e.g. TTL, LVDS, voltage referenced) in parallel. In the shown diagram that focusses on signal flow rather than IO standards, the input stage(s) would be located in the said block.

 

[zian]

Simply consider that FPGA inputs have either a single configurable input stage or multiple input stages for different IO standards (e.g. TTL, LVDS, voltage referenced) in parallel. In the shown diagram that focusses on signal flow rather than IO standards, the input stage(s) would be located in the said block.

Yes, it's possible.
So I will come back here after my testing on 10 inputs (or more if needed) between 0.8V and 1.7V to present results and validate or unvalidate (or don't determine) the different assumptions.
I've to find before a low cost FPGA board to be potentially damaged.
Thanks evby for your answers !