cen199
Newbie
I encountered a very strange issue with a Cyclone II design from 2014. I am wondering if the FPGA configuration is being corrupted after 4 to 6 hours running. According to Altera AN357, the CRC check can be read from user logic and "To access the logic array, the _crcblock WYSIWYG atom must be inserted into the design."
There is also an example in AN357:
cycloneii_crcblock <crcblock_name>
(
.clk(<clock source>),
.shiftnld(<shiftnld source>),
.ldsrc(<ldsrc source>),
.crcerror(<crcerror out destination>),
.regout(<output destination>)
);
I have been using a small subset of VHDL and a top level .bdf schematic to design for quite a while. Unfortunately, I must have skipped over some FPGA basics because I have no idea what to do with the example.
How can I create a .bsf symbol file from the example?
I realize that having user code check for corrupted user code is less than ideal, but the CRC_ERROR pin is already used for another purpose in the design.
There is also an example in AN357:
cycloneii_crcblock <crcblock_name>
(
.clk(<clock source>),
.shiftnld(<shiftnld source>),
.ldsrc(<ldsrc source>),
.crcerror(<crcerror out destination>),
.regout(<output destination>)
);
I have been using a small subset of VHDL and a top level .bdf schematic to design for quite a while. Unfortunately, I must have skipped over some FPGA basics because I have no idea what to do with the example.
How can I create a .bsf symbol file from the example?
I realize that having user code check for corrupted user code is less than ideal, but the CRC_ERROR pin is already used for another purpose in the design.