Integrator Saturation in Delta Sigma modulator.

[engrMunna]

Hi, I am trying out a 1st order delta sigma modulator, in current domain, The problem is that the voltage at the node to which my integrating capacitor is connected keeps ramping up. I have a differential implementation and and the voltage at these input node ramp in the opposite direction. And the loop cannot recover from overloading. Thank!

 

[FvM]

Wrong feedback polarity? You would want to show a schematic.

 

[engrMunna]

Wrong feedback polarity? You would want to show a schematic.

No. I checked the polarities, they are ok....the other thing is that I am not using a conventional comparator based quantizer. Its an oscillator whose frequency is controlled but the error signal coming out of the Filters.

In the same structure when I use a comparator based quantizer , it gives the required noise shaping, but the level of the input to the quantizer(coming out of the filter) is periodic waveform with the values going above the overloading level in each cycle.

I am attaching a picture of the two signals coming out of the integrator....they should be differential but as I see...they are not...i mean they seem out of phase but are not truly differential. Can this be a problem?

 

[engrMunna]

As you can see thee currents are clipped of at zero...the circuit is sourcing current but can not sink it.....I'll try to recitfy this problem first...but if you have any other pointers please share them Thanks