Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

integrated inductor design and simulation

Status
Not open for further replies.
A

amir88

Advanced Member level 4
Joined
Nov 4, 2009
Messages
118
Helped
13
Reputation
26
Reaction score
8
Trophy points
1,298
Location
bandarabbas
Activity points
1,926
Hi everybody,

I assume I'm using CMOS technology and I want to design a passive inductor.

1. Do I have to last metal for designing an integrated inductor? if my process has got 8 metal layers, then I have to use metal layer 7 and 8?
2.How can I quickly design an inductor for cadence for example a 2 nH inductor in gpdk90nm?
3. Is there any tutorial for integrated inductor design especially in cadence, a layout tutorial is appreciated?


thanks in advance
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top