Integrated Clock Gating Cell - Timing Constraints

[iammituraj]

I have a negative latch based IGC like this in clock path which takes care of glitch on switching gate.

'gate' is coming from another clock domain sysclk. All clocks (clk, sysclk) are defined in SDC. Do I have to add any additional constraints here like clock gating check? I have a feeling whether I have to create a generated clock at the output of IGC.

 

[ThisIsNotSam]

the ICG cell will have these described in the LIB file, you do not need to add separate constraints. the same way we do not write setup/hold constraints for individual flops.

 

[iammituraj]

the ICG cell will have these described in the LIB file, you do not need to add separate constraints. the same way we do not write setup/hold constraints for individual flops.

Thanks for the response. What about generated clock? Should I create it at ICG output with same period as clk?

 

[ThisIsNotSam]

not needed either. it is all managed automatically for you.

 

[maulin sheth]

Generally, we define async clock between different clock domains.
If gate is driven from different async clock domain then path will become false path.

Why do you want to define generated clock at output of CGC?